Patents by Inventor Jack R. Smith

Jack R. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210033660
    Abstract: An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Sebastian T. Ventrone, Richard S. Graf, Ezra D. B. Hall, Jack R. Smith
  • Publication number: 20170255471
    Abstract: Various embodiments include processors for processing operations. In some cases, a processor includes: an instruction fetch component configured to fetch processing instructions; an instruction cache component connected with the instruction fetch component, configured to store the processing instructions; an execution component connected with the instruction cache component, configured to execute the processing instructions; a monitor component connected with the execution component, configured to receive execution results from the processing instructions; and a content addressable memory (CAM) component connected with the instruction fetch component and the monitor component, wherein the monitor component stores a portion of the execution results in the CAM for subsequent use in bypassing the execution component.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 7, 2017
    Inventors: Jack R. Smith, Sebastian T. Ventrone, Ezra D. B. Hall
  • Patent number: 9299590
    Abstract: Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Ezra D. B. Hall, Vibhor Jain, Jack R. Smith, Sebastian T. Ventrone
  • Patent number: 9201654
    Abstract: Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jason F. Cantin, Jack R. Smith, Arnold S. Tran, Kenichi Tsuchiya
  • Patent number: 8988140
    Abstract: An integrated circuit includes logic regions and dynamically adjustable voltage controllers. A voltage controller connected to each logic region enables voltage adjustment while the chip is operating. Each voltage controller has a selector device connected to voltage input lines providing different voltages. A voltage sensor connected to the output of the selector device provides a supply voltage to one of the logic regions. A control circuit dynamically monitors the supply voltage, captures and stores a digital representation of the supply voltage during each cycle of a clock, and tracks variations over time, based on operation of the logic regions. When variations in the supply voltage exceed an operational threshold of one of the logic regions, the control circuit submits a request to a central controller. When the central controller grants permission, the control circuit dynamically adjusts the voltage by enabling the selector device to choose a different voltage input line.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Richard S. Graf, Joseph A. Iadanza, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone, Ivan L. Wemple
  • Publication number: 20150002217
    Abstract: An integrated circuit includes logic regions and dynamically adjustable voltage controllers. A voltage controller connected to each logic region enables voltage adjustment while the chip is operating. Each voltage controller has a selector device connected to voltage input lines providing different voltages. A voltage sensor connected to the output of the selector device provides a supply voltage to one of the logic regions. A control circuit dynamically monitors the supply voltage, captures and stores a digital representation of the supply voltage during each cycle of a clock, and tracks variations over time, based on operation of the logic regions. When variations in the supply voltage exceed an operational threshold of one of the logic regions, the control circuit submits a request to a central controller. When the central controller grants permission, the control circuit dynamically adjusts the voltage by enabling the selector device to choose a different voltage input line.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Richard S. Graf, Joseph A. Iadanza, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone, Ivan L. Wemple
  • Publication number: 20140353955
    Abstract: The ROPS comprises a highly rigid behind-cab-frame, a mounting-plate of which is bolted to the truck chassis. A roof-canopy is integrated into the frame. The ROPS includes a brace which holds the frame upright, and ensures that the roof-canopy remains in position, protecting the cab, during rollover. The frame is bolted into the chassis using the same bolts that hold the cargo-box to the chassis (or longer bolts), whereby installation is quick and easy. The installed ROPS is held fast to the chassis of the truck with great strength and rigidity, but there is no disruption to the structural integrity of the chassis.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Applicants: Stanley Appleton Corporation
    Inventors: Sahil BHARDWAJ, Jack R. Smith
  • Patent number: 8899620
    Abstract: The ROPS comprises a highly rigid behind-cab-frame, a mounting-plate of which is bolted to the truck chassis. A roof-canopy is integrated into the frame. The ROPS includes a brace which holds the frame upright, and ensures that the roof-canopy remains in position, protecting the cab, during rollover. The frame is bolted into the chassis using the same bolts that hold the cargo-box to the chassis (or longer bolts), whereby installation is quick and easy. The installed ROPS is held fast to the chassis of the truck with great strength and rigidity, but there is no disruption to the structural integrity of the chassis.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: December 2, 2014
    Inventors: Sahil Bhardwaj, Jack R. Smith
  • Patent number: 8756549
    Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Richard S. Graf, Keishi Okamoto, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
  • Patent number: 8612815
    Abstract: Disclosed are integrated circuits that incorporate an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. Specifically, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
  • Publication number: 20130159803
    Abstract: Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: International Business Machines Corporation
    Inventors: Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
  • Patent number: 8381050
    Abstract: The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Pamela S. Gillis, Jack R. Smith, Tad J. Wilder, Francis Woytowich, Tian Xia
  • Publication number: 20130007425
    Abstract: Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jason F. Cantin, Jack R. Smith, Arnold S. Tran, Kenichi Tsuchiya
  • Patent number: 8300752
    Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, David W. Milton, Clarence R. Ogilvie, Jack R. Smith
  • Publication number: 20120168416
    Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 5, 2012
    Applicant: International Business Machines Corporation
    Inventors: Richard S. Graf, Keishi Okamoto, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
  • Patent number: 8188765
    Abstract: Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael R. Ouellette, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
  • Patent number: 8189723
    Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, David W. Milton, Clarence R. Ogilvie, Jack R. Smith
  • Publication number: 20120062300
    Abstract: Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 15, 2012
    Applicant: International Business Machines Corporation
    Inventors: Michael R. Ouellette, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone
  • Publication number: 20110307661
    Abstract: An integrated circuit chip having plural processors with a shared field programmable gate array (FPGA) unit, a design structure thereof, and method for allocating the shared FPGA unit. A method includes storing a plurality of data that define a plurality of configurations of a field programmable gate array (FPGA), wherein the FPGA is arranged in the execution pipeline of at least one processor; selecting one of the plurality of data; and programming the FPGA based on the selected one of the plurality of data.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 15, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack R. SMITH, Sebastian T. VENTRONE
  • Publication number: 20110121838
    Abstract: The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.
    Type: Application
    Filed: November 25, 2009
    Publication date: May 26, 2011
    Applicant: International Business Machines Corporation
    Inventors: Pamela S. Gillis, Jack R. Smith, Tad J. Wilder, Francis Woytowich, Tian Xia