Abstract: The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.

Abstract: A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between the first and second storage regions. When the function is parsed into a plurality of functional blocks, this configuration allows the RLA to process the function by sequentially processing the functional blocks in alternating directions within the RLA, using the plurality of programmable logic elements to sequentially process each of the functional blocks and using the first and second storage regions to temporarily hold the input and output for that one of the functional blocks.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a state of a delayed remote clock signal on the remote clock delay line; and a control that influences a delay associated with the data delay line and the remote clock delay line.

Abstract: A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficiency for communicating with the memory. In particular, a register can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache, multiple ways of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task, a processor, and/or a performance evaluation.

Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

Abstract: A bus protocol that allows a master to transfer the same data to multiple devices at the same time. More specifically, the bus protocol uses a particular voltage level to identify whether a device should receive the data. A controller is used for programming the voltage levels for the various devices.

Abstract: A new hardware description language (HDL) extension at the register-transfer level (RTL) for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for the fault tolerant logic functions. Code (20) is written in VHDL at the RTL and includes instructions for adding the operator “FT” to certain logic functions. Logic functions that include the FT operator are considered critical functions, i.e., fault tolerant. By including the FT operator, a logic synthesis tool is alerted to the functions that have been designated as fault tolerant. As a result, the preprogrammed logic synthesis tool causes the design of the IC to include a fault redundant scheme (30) for the logic functions that include the FT operator. Fault redundant scheme (30) includes three copies of the logic function, i.e., Copy A (32), Copy B (34), and Copy C (36), as well as a majority voter 38.

Abstract: A method and system for modifying the function of a state machine having a programmable logic device. The method includes the steps of modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; generating a programmable logic device netlist from differences in the high-level design and the high-level modified design; and installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.

Abstract: The disclosure presents a method of designing an integrated circuit having latches. The invention first prepares a logical design of logic devices and latches and then creates a physical design by positioning the logic devices and the latches within the integrated circuit based on the logical design. During the process of creating the physical design the invention eliminates redundant latches by combining latches which do not transition during the same clock cycle, latches which do not relate to the same logical function, latches which are in the same clock domain, and latches that are within a given physical proximity of each other.

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract: A bus protocol that allows a master to transfer the same data to multiple devices at the same time. More specifically, the bus protocol uses a particular voltage level to identify whether a device should receive the data. A controller is used for programming the voltage levels for the various devices.

Abstract: A data processing system (20) having a synchronous interface and partitioned clock and I/O logic controller structure. The system includes a plurality of processing components (22), each having a plurality of I/O logic controllers (24). In addition, the system includes a plurality of clock sources (30) for providing clock signals and a plurality of multiplexers (36) connected to said plurality of clock sources and to at least two of said I/O logic controllers. The clock signals differ from one another in frequency or in skew, i.e., time delay. By appropriate control of clock select registers connected to the plurality of multiplexers, one of the plurality of clock signals from the clock sources may be provided to the two or more I/O logic controllers connected to a given multiplexer. This permits different groups of I/O logic controllers to receive different clock signals in parallel.

Abstract: A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.

Abstract: A forward facing rowing mechanism (10) for a boat (11) having a bow (12), a longitudinal axis (A.sub.1) and both port and starboard gunwales (21). A mounting bracket (20) is adapted to be supported from each gunwale (21), and a tilting frame (25) is supported from the mounting bracket (20) for pivotal movement about an axis (A.sub.2) substantially parallel to the longitudinal axis (A.sub.1) of the boat (11). A drive sub-assembly (31.sub.x) is carried on the tilting frame (25) to be pivotal about a first angular rotational axis (A.sub.3). A driven sub-assembly (31.sub.y) is carried on the tilting frame (25) to be pivotal about a second angular rotational axis (A.sub.4). A handle (14) is secured to the drive sub-assembly (31.sub.x) for rotation about a first feathering axis (A.sub.5). A blade (18) is secured to the driven sub-assembly (31.sub.y) for rotation about a second feathering axis (A.sub.6). A first drive (83 and 84) interconnects the drive and driven sub-assemblies (31.sub.x and 31.sub.

Abstract: An electric power plant, including a fossil fired boiler and a steam turbine, is operated by a control system including a plant unit master. The control system includes a boiler control for determining the inputs of fuel, air and water, and a turbine control for determining the position of the throttle valves introducing steam from the boiler to the turbine. The plant unit master provides a load demand reference in parallel to the boiler control and to the turbine control, whereby the turbine and the boiler are operated in a coordinated manner. Measuring means provide indications of throttle pressure, power generated by the system and turbine rotor speed. Distinct controllers, each including a controller and responsive to one of the aforementioned indications and its corresponding reference, modify the load demand reference before it is applied to the turbine control or to the boiler control.