Patents by Inventor Jack Yeh

Jack Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11714141
    Abstract: A method for determining a connection status of a device to a cable within a network environment is provided. The method comprises obtaining a signal from a non-data carrying wire of the cable by a detector that is digitally isolated from data transmitted in a data carrying wire of the cable within the network environment, modifying the signal transmitted by the non-data carrying wire to the device and evaluating the modified signal to determine a connection status of the device to the cable.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: August 1, 2023
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Patrick Jacques Andre Marie Daney De Marcillac, Sandro Secci, Rudolf Wegener, Jack Yeh, Joshua Serratelli Schiffman
  • Publication number: 20220057459
    Abstract: A method for determining a connection status of a device to a cable within a network environment is provided. The method comprises obtaining a signal from a non-data carrying wire of the cable by a detector that is digitally isolated from data transmitted in a data carrying wire of the cable within the network environment, modifying the signal transmitted by the non-data carrying wire to the device and evaluating the modified signal to determine a connection status of the device to the cable.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 24, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Patrick Jacques Andre Marie Daney De Marcillac, Sandro Secci, Rudolf Wegener, Jack Yeh, Joshua Serratelli Schiffman
  • Publication number: 20210266366
    Abstract: Systems, methods, architectures, and computer program products for linking multiple devices are disclosed. In an example for linking a mobile device with a desktop device, an identifier of a mobile device can be received from a desktop computer. The identifier can be used to send a link to the mobile device. When the link is accessed, a code and a channel are generated. The mobile device is connected to the channel and the code is provided to the mobile device. The code is entered at the desktop device and the desktop device is connected to the channel responsive to the code being validated, thereby linking the desktop and mobile devices.
    Type: Application
    Filed: October 8, 2020
    Publication date: August 26, 2021
    Inventors: Rush L. Bartlett, II, Kan-Yueh Chen, Ching-Cheng Chou, David Lin, Po-Min Lin, I-Chien Liu, Matthew S. Taylor, Ryan J.F. Van Wert, Frank Wang, Jack Yeh, Tsung-Wei Wang
  • Patent number: 10826997
    Abstract: Systems, methods, architectures, and computer program products for linking multiple devices are disclosed. In an example for linking a mobile device with a desktop device, an identifier of a mobile device can be received from a desktop computer. The identifier can be used to send a link to the mobile device. When the link is accessed, a code and a channel are generated. The mobile device is connected to the channel and the code is provided to the mobile device. The code is entered at the desktop device and the desktop device is connected to the channel responsive to the code being validated, thereby linking the desktop and mobile devices.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 3, 2020
    Assignee: VYNCA, INC.
    Inventors: Rush L. Bartlett, II, Kan-Yueh Chen, Ching-Cheng Chou, David Lin, Po-Min Lin, I-Chien Liu, Matthew S. Taylor, Ryan J. F. Van Wert, Frank Wang, Jack Yeh, Tsung-Wei Wang
  • Publication number: 20170135142
    Abstract: Systems, methods, architectures, and computer program products for linking multiple devices are disclosed. In an example for linking a mobile device with a desktop device, an identifier of a mobile device can be received from a desktop computer. The identifier can be used to send a link to the mobile device. When the link is accessed, a code and a channel are generated. The mobile device is connected to the channel and the code is provided to the mobile device. The code is entered at the desktop device and the desktop device is connected to the channel responsive to the code being validated, thereby linking the desktop and mobile devices.
    Type: Application
    Filed: November 2, 2016
    Publication date: May 11, 2017
    Inventors: Rush L. Bartlett, II, Kan-Yueh Chen, Ching-Cheng Chou, David Lin, Po-Min Lin, I-Chien Liu, Matthew S. Taylor, Ryan J.F. Wert, Frank Wang, Jack Yeh
  • Publication number: 20160328523
    Abstract: A method for providing access to patient information from within an electronic medical record may involve: receiving, from a user, at least one piece of identifying information, identifying the user as a person authorized to access the patient information; providing an encrypted link on an electronic medical record of the patient, wherein the encrypted link is preloaded with the at least one piece of identifying information and a patient medical record number corresponding to the patient; decrypting the encrypted link in response to the user clicking on the encrypted link, without requiring the user to provide any further identifying information; and providing the patient information to the user via a secure web site, in response to the user clicking on the link.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 10, 2016
    Inventors: Rush L. Bartlett, II, David Lin, Jack Yeh, Ryan J.F. Van Wert, Frank T. Wang
  • Publication number: 20150294068
    Abstract: A method for providing access to patient information from within an electronic medical record may involve: receiving, from a user, at least one piece of identifying information, identifying the user as a person authorized to access the patient information; providing an encrypted link on an electronic medical record of the patient, wherein the encrypted link is preloaded with the at least one piece of identifying information and a patient medical record number corresponding to the patient; decrypting the encrypted link in response to the user clicking on the encrypted link, without requiring the user to provide any further identifying information; and providing the patient information to the user via a secure web site, in response to the user clicking on the link.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 15, 2015
    Inventors: Rush L. BARTLETT, II, David Lin, Ryan J.F. Van Wert, Frank T. Wang, Jack Yeh
  • Publication number: 20090298658
    Abstract: A power tool driver includes a tool magazine having a cartridge that enables a change of tools in the power tool driver done in a convenient and safe way. The cartridge is selectively moveable and having a plurality of slots for accommodating a plurality of tools respectively, in which one of the tools can be selected to incorporate with the power tool driver.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Inventor: Jack Yeh
  • Patent number: 7514740
    Abstract: A non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: April 7, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsun Hsu, Yung-Tao Lin, Derek Lin, Jack Yeh
  • Patent number: 7417278
    Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: August 26, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo, Hung-Cheng Sung, Jack Yeh
  • Publication number: 20080006868
    Abstract: A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 10, 2008
    Inventors: Te-Hsun Hsu, Yung-Tao Lin, Derek Lin, Jack Yeh
  • Publication number: 20070038222
    Abstract: A repair system including a closure prosthesis and deployment device, and associated methods for repairing any imperfection including a flaw, hole, tear, bulge, or, in some cases, a deliberate cut or incision in any tissue including an intervertebral disc is disclosed. The prosthesis has first and second side portions with a connecting central portion, and is designed to span an imperfection with opposite ends positioned on opposite sides of the imperfection or the same side of the imperfection. The prosthesis may include anchoring features including barbs and/or members that extend transversely or at different angles. The deployment device can include a cannula for positioning the prosthesis near the imperfection, and, in some cases, a mechanism that may cause the two sides of the prosthesis to be deployed in a specific order.
    Type: Application
    Filed: April 24, 2006
    Publication date: February 15, 2007
    Applicant: JMEA Corporation
    Inventors: Mohit Bhatnagar, Jack Yeh, Jim Sack, Richard Woods
  • Publication number: 20060247643
    Abstract: A repair system including a closure prosthesis and deployment device, and associated methods for repairing any imperfection including a flaw, hole, tear, bulge, or, in some cases, a deliberate cut or incision in any tissue including an intervertebral disc. The prosthesis has first and second side portions with a connecting central portion, and is designed to span an imperfection with opposite ends positioned on opposite sides of the imperfection. The prosthesis may include anchoring features including barbs and/or members that extend transversely. The deployment device can include a canula for positioning the prosthesis near the imperfection, and, in some cases, a mechanism that may cause the two sides of the prosthesis to be deployed in a specific order.
    Type: Application
    Filed: April 29, 2005
    Publication date: November 2, 2006
    Applicant: JMEA Corporation
    Inventors: Mohit Bhatnagar, Jack Yeh, James Sack, Richard Woods
  • Publication number: 20060247644
    Abstract: A repair system including a closure prosthesis and deployment device, and associated methods for repairing any imperfection including a flaw, hole, tear, bulge, or, in some cases, a deliberate cut or incision in any tissue including an intervertebral disc. The prosthesis has first and second side portions with a connecting central portion, and is designed to span an imperfection with opposite ends positioned on opposite sides of the imperfection. The prosthesis may include anchoring features including barbs and/or members that extend transversely. The deployment device can include a canula for positioning the prosthesis near the imperfection, and, in some cases, a mechanism that may cause the two sides of the prosthesis to be deployed in a specific order.
    Type: Application
    Filed: January 3, 2006
    Publication date: November 2, 2006
    Inventors: Mohit Bhatnagar, Jack Yeh, James Sack, Richard Woods
  • Patent number: 7001809
    Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: February 21, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo, Hung-Cheng Sung, Jack Yeh
  • Patent number: 6982458
    Abstract: A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 3, 2006
    Assignee: Taiwan Semiconductor Maufacturing Co., LTD
    Inventors: Wen-Ting Chu, Jack Yeh, Chrong-Jung Lin
  • Publication number: 20050207264
    Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.
    Type: Application
    Filed: May 5, 2005
    Publication date: September 22, 2005
    Inventors: Chia-Ta Hsieh, Yai-Fen Lin, Di-Son Kuo, Hung-Cheng Sung, Jack Yeh
  • Patent number: 6902978
    Abstract: A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: June 7, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Ting Chu, Jack Yeh, Chrong-Jung Lin
  • Publication number: 20050029575
    Abstract: A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 10, 2005
    Inventors: Wen-Ting Chu, Jack Yeh, Chrong-Jung Lin
  • Publication number: 20050026368
    Abstract: A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 3, 2005
    Inventors: Wen-Ting Chu, Jack Yeh, Chrong-Jung Lin