Abstract: A memory circuit includes first and second read-only memory (ROM) cells aligned along a first active structure including a first shared source portion of the first and second ROM cells, third and fourth ROM cells aligned along a second active structure including a second shared source portion of the third and fourth ROM cells, a first bit line overlying the first and second ROM cells, a second bit line overlying the third and fourth ROM cells, and a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines. A conductive structure is electrically connected to each of the first and second shared source portions and the reference voltage line and is positioned in a metal layer below the same metal layer.

Abstract: A memory circuit includes first and second active structures extending along a first direction. The first active structure has a shared source portion and first and second drain portions corresponding to source and drain nodes of first and second memory cells. The second active structure has a shared source portion and third and fourth drain portions corresponding to source and drain nodes of third and fourth memory cells. A first conductive structure extends along a second direction and electrically connects the shared source portions of the first and second active structures, and first and second bit lines extend over the first and second active structures. A via plug is part of a direct electrical connection between the first bit line and one of the first or second drain portions or between the second bit line and one of the third or fourth drain portions.

Abstract: A memory circuit includes: memory cells each including a storage transistor corresponding to a predetermined configuration; and a tracking circuit configured to elapse a variable waiting period during which a voltage on a first node decreases from a first level to a second level, the tracking circuit including a first finger circuit coupled between a first node of a tracking bit line and a reference voltage node, the first finger circuit including a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with a tracking word line; and a second finger circuit coupled between the first node and the reference voltage node; and a first switch configured to adjust the variable waiting period by selectively coupling the second finger circuit in parallel with the first finger circuit.

Abstract: A method, includes: in a strap cell disposed between a memory cell and a logic cell, arranging a first gate across an active region; arranging a second gate next to and in parallel with the first gate and at an end of the active region; and when at least one conductive segment has a first length, arranging the at least one conductive segment across the first gate, the second gate, and no dummy gate in the strap cell. A semiconductor device is also disclosed herein.

Abstract: A memory circuit includes: memory cells each including a storage transistor corresponding to a predetermined configuration; and a tracking circuit configured to elapse a variable waiting period during which a voltage on a first node decreases from a first level to a second level, the tracking circuit including a first finger circuit coupled between a first node of a tracking bit line and a reference voltage node, the first finger circuit including a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with a tracking word line; and a second finger circuit coupled between the first node and the reference voltage node; and a first switch configured to adjust the variable waiting period by selectively coupling the second finger circuit in parallel with the first finger circuit.

Abstract: A memory circuit includes first and second active structures extending along a first direction. The first active structure has a shared source portion and first and second drain portions corresponding to source and drain nodes of first and second memory cells. The second active structure has a shared source portion and third and fourth drain portions corresponding to source and drain nodes of third and fourth memory cells. A first conductive structure extends along a second direction and electrically connects the shared source portions of the first and second active structures, and first and second bit lines extend over the first and second active structures. A via plug is part of a direct electrical connection between the first bit line and one of the first or second drain portions or between the second bit line and one of the third or fourth drain portions.

Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.

Abstract: A method includes placing first and second oxide diffusion (OD) layout patterns in a layout design corresponding to first, second, third, and fourth memory cells of a memory circuit. The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. The method is wholly or partially performed by using a hardware processor.

Abstract: A memory circuit includes: memory cells each including a storage transistor having a first configuration; and a tracking circuit including: a tracking bit line having first and second intermediary nodes; a tracking word line; a first finger circuit (coupled between the first intermediary node and a reference voltage node) including: a first set of first tracking cells, each including a first shadow transistor having the first configuration; and a second finger circuit (coupled between the second intermediary node and the reference voltage node) including: a second set of second tracking cells, each including a second shadow transistor having the first configuration; gate terminals of the first and second shadow transistors being coupled with the tracking word line; and a switch configured to selectively couple the first intermediary node with the second intermediary node and thereby selectively couple the first and second finger circuits in parallel.

Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.

Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.

Abstract: A memory circuit includes: memory cells each including a storage transistor having a first configuration; and a tracking circuit including: a tracking bit line having first and second intermediary nodes; a tracking word line; a first finger circuit (coupled between the first intermediary node and a reference voltage node) including: a first set of first tracking cells, each including a first shadow transistor having the first configuration; and a second finger circuit (coupled between the second intermediary node and the reference voltage node) including: a second set of second tracking cells, each including a second shadow transistor having the first configuration; gate terminals of the first and second shadow transistors being coupled with the tracking word line; and a switch configured to selectively couple the first intermediary node with the second intermediary node and thereby selectively couple the first and second finger circuits in parallel.

Abstract: A method includes placing first and second oxide diffusion (OD) layout patterns in a layout design corresponding to first, second, third, and fourth memory cells of a memory circuit. The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. The method is wholly or partially performed by using a hardware processor.

Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.

Abstract: A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value.

Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.

Abstract: A memory circuit layout design includes first, second, third, and fourth memory cell regions abutting one another and corresponding to respective first, second, third, and fourth memory cells of the memory circuit. A first oxide diffusion (OD) layout pattern corresponds to a first active structure for forming the first and second memory cells, extends along a first direction, and has a shared source portion overlapping the first and second memory cell regions. A second OD layout pattern corresponds to a second active structure for forming the third and fourth memory cells, extends along the first direction, and has a shared source portion overlapping the third and fourth memory cell regions. A first conductive layout pattern corresponds to a first conductive structure under a lowest via plug layer of the memory circuit, extends along a second direction, and overlaps the shared source portions of the first and second OD layout patterns.

Abstract: A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer is coupled to the first control line and the first control line is isolated from the second control line. A second layout section is inserted at every N-th first layout section, N being a positive integer equal to or greater than 2. The second layout section includes the first control line, the second control line and a lower conductive line in the second metal layer coupled to the second control line and to an upper conductive line in the third metal layer. The lower conductive lines in the first and second layout sections are isolated from each other.

Abstract: A read-only memory (ROM) device includes a memory cell that is electrically coupled to a bitline (BL) or to a BL which represents a complement of the BL. The ROM device precharges the BL and the BL to a first logical value. The ROM device activates the memory cell which discharges the BL when the memory cell is coupled to the BL or discharges the BL when the memory cell is coupled to the BL. The ROM device reads the first logical value as being stored within the memory cell when the BL is less than the BL. Otherwise, the ROM device reads the second logical value as being stored within the memory cell when the BL is greater than the BL.

Abstract: A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value.