Abstract: The invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions. A crown-liked conductive plate is formed over an insulation oxide layer and a contact plug. The crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug. The crown-like conductive plate, served as the bottom plate for a DRAM capacitor, is composed of tungsten silicide or a combination of a tungsten nitride layer and a tungsten layer.

Abstract: A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.

Abstract: A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.

Abstract: A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.

Abstract: A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.

Abstract: An improved formation method produces a metallic fuse capable of lowering the laser power needed for carrying out circuit repair. The method includes forming a metallic fuse when the penultimate metallic layer is formed. Since the metallic fuse is not too far away from the top surface, the power of the laser beam necessary for repairing the circuit can be moderate. Furthermore, the laser beam is more focused because it travels a shorter distance to reach the fuse, thereby avoiding unnecessary dispersion through intermediate material. Moreover, since the metallic fuse itself is not too thick, only a low-power laser beam is needed to melt the metallic fuse.

Abstract: A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.

Abstract: A device and method for mechanically cleaning the surface of the root of the human tongue, the device including a cleaning head configured for entry between the soft palate and the surface of the human tongue root, and having abrasive means for mechanically removing pathological microorganisms from the surface of the tongue root, and a handle connected to the cleaning head for manipulation thereof, wherein the device has an overall maximum height at the cleaning head of no more than approximately 15 mm, and wherein the cleaning head is concavely bent. The method includes closing the lips to the rest position about the handle, so as to reduce the gag reflex and to position the handle and the cleaning head generally parallel to the tongue, and providing a relative motion between the cleaning head and the surface of the tongue root by reciprocally pivoting the cleaning head.

Abstract: An integrated circuit device having both an array of logic circuits and an array of embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions of the logic FETs are subjected to a salicide process at this initial phase and a thick planarized oxide layer is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias are formed to expose each of the source drain regions of the DRAM transfer FETs and to expose select conductors within the logic circuits.

Abstract: A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.

Abstract: A magazine assembly for a pneumatic staple gun, including a magazine base, a mounting plate fixedly secured to the magazine base having one end covered over the bottom side of the magazine base and an opposite end connected to the gun body of the pneumatic staple gun, a magazine cover covered on the magazine base at one side, a hooked stop plate fixedly secured to the rear end of the magazine base, an end block fixedly secured to the rear end of the magazine cover, and a constraint member turned about a pivot on the end block and having a lever at one end supported on a return spring and a hook at an opposite end detachably hooked up with the hooked stop plate.

Abstract: An exhaust hood mounting structure for pneumatic nail guns, including an exhaust hood mounted on the exhaust port of a pneumatic nail gun and having a center countersunk hole, a locating cup mounted within the center countersunk hole on the exhaust hood and having a center through hole, a screw inserted through the center through hole on the locating cup and the center countersunk hole on the exhaust hood and then threaded into a screw hole on the pneumatic nail gun within the exhaust port, wherein a corrugated spring is mounted around the screw and retained between the exhaust hood and the locating cup for permitting the exhaust hood to be turned round the screw to the desired angle by hand and retained in the adjusted position when released from hand.

Abstract: A single-shooting/continuous-shooting control switch installed in a pneumatic nail gun for controlling the firing of nails, the control switch including a first valve seat connected to a pneumatic pressure source, a second valve seat connected between the first valve seat and the firing pin of the pneumatic nail gun, a first valve rod moved by the trigger of the pneumatic nail gun to control the air passage between the first air valve seat and the second air valve seat, a second valve rod moved by the trigger of the pneumatic nail gun to control the air passage between the second air valve seat and the firing pin, and a stop block turned about the first valve rod between between a first position for letting the first valve rod be lifted by the trigger to stop the passage between the first air passage and the second air passage for a single-shooting operation, and a second position to stop the trigger from lifting the first valve rod for letting pneumatic pressure be continuosuly drawn from the first air valve