Abstract: Systems and techniques include identifying a network layer for performing a memory operation, identifying a subset of a plurality of configuration bit clusters of a non-volatile distributed memory that are mapped to the identified network layer using a cluster mapping, in response to identifying the subset of the plurality of configuration bit clusters, activating the subset of the plurality of configuration bit clusters, loading network component data from the subset of the plurality of configuration bit clusters into a local buffer, and applying the network component data to the network layer for performing the memory operation.

Abstract: Various embodiments of the systems, methods, and devices are provided for controlled operation of IVL for breaking up calcified lesions in an anatomical conduit. More specifically, control arrangements are disclosed concerning managing and/or providing electrical energy to generate an electrical arc between a set of spaced-apart electrodes disposed within a fluid-filled balloon, creating stable and constant, or slightly increasing, pressure output over at least 300 voltage pulses. Control arrangements disclosed further determine whether an electrical arc was successfully generated.

Abstract: A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.

Abstract: An apparatus for cryostorage and manipulation of a plurality of container units includes a cryochamber having a cryo-access port. The cryochamber is electrically cooled at cryogenic temperatures. A unit holder is located inside the cryochamber and is configured to hold a plurality of container units. A user access area is provided for selectively permitting access to a chosen container unit by an authenticated user who has been authenticated by the apparatus. A motive grasper is provided for selectively removing the chosen container unit from the cryochamber through the cryo-access port, and selectively placing the chosen container unit into the user access area.

Abstract: Various embodiments of the systems, methods, and devices are provided for controlled operation of an intravascular lithotripsy (“IVL”) system for breaking up calcified lesions in an anatomical conduit. More specifically, control arrangements are disclosed concerning managing and/or providing electrical energy to generate an electrical arc between a set of spaced-apart electrodes disposed within a fluid-fillable member, wherein the IVL system may be powered by an AC power source and/or a DC power source.

Abstract: Various embodiments of the systems, methods, and devices are provided for controlled operation of an intravascular lithotripsy system for breaking up calcified lesions in an anatomical conduit. More specifically, control arrangements are disclosed concerning managing and/or providing electrical energy to generate an electrical arc between a set of spaced-apart electrodes disposed within a fluid-filled member configured to contain a conductive fluid.

Abstract: Various embodiments of the systems, methods, and devices are provided for controlled operation of an intravascular lithotripsy system for breaking up calcified lesions in an anatomical conduit. More specifically, control arrangements are disclosed concerning managing and/or providing electrical energy to generate an electrical arc between a set of spaced-apart electrodes disposed within fluid-fillable member are disclosed.

Abstract: Various embodiments of the systems, methods, and devices are provided for controlled operation of an intravascular lithotripsy (“IVL”) system for breaking up calcified lesions in an anatomical conduit. More specifically, control arrangements are disclosed concerning managing and/or providing and/or assessing the electrical energy needed to generate an electrical arc between a set of spaced-apart electrodes disposed within a fluid-fillable member.

Abstract: A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.

Abstract: An apparatus for cryostorage and manipulation of a plurality of container units includes a cryochamber having a cryo-access port. The cryochamber is electrically cooled at cryogenic temperatures. A unit holder is located inside the cryochamber and is configured to hold a plurality of container units. A user access area is provided for selectively permitting access to a chosen container unit by an authenticated user who has been authenticated by the apparatus. A motive grasper is provided for selectively removing the chosen container unit from the cryochamber through the cryo-access port, and selectively placing the chosen container unit into the user access area.

Abstract: A memory includes an array of resistive memory cells and circuitry for setting a write parameter for improving write effectiveness to the cells of the memory array. The circuitry performs a write parameter setting routine that determines a midpoint resistance of a memory state of cells of the array and determines a write efficiency of a weak write operation to cells of the array. Based on the determined midpoint resistance and the determined write efficiency, the circuit sets a write parameter level for subsequent writes to cells of the array.

Abstract: An apparatus for cryostorage and manipulation of a plurality of container units includes a cryochamber having a cryo-access port. The cryochamber is electrically cooled at cryogenic temperatures. A unit holder is located inside the cryochamber and is configured to hold a plurality of container units. A user access area is provided for selectively permitting access to a chosen container unit by an authenticated user who has been authenticated by the apparatus. A motive grasper is provided for selectively removing the chosen container unit from the cryochamber through the cryo-access port, and selectively placing the chosen container unit into the user access area.

Abstract: A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.

Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.

Abstract: A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.

Abstract: A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuity to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.

Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.

Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.

Abstract: As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.