Abstract: A memory controller for strobe-based memory systems is disclosed. The memory controller includes a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit includes an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.

Abstract: A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.

Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

Abstract: Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

Abstract: Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.

Abstract: A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

Abstract: A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.

Abstract: A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.

Abstract: A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.

Abstract: A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: A method is disclosed comprising detecting an edge-transition of a strobe signal using hysteresis, the strobe signal originating in a first clock domain. A count is controlled in a first direction in response to the detected edge-transition. The count is controlled in a second direction in response to an edge-transition of a clock signal, the clock signal originating in a second clock domain. Data is interfaced between the first and second clock domains in response to the count.

Abstract: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

Abstract: A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data signal lines and to a portion of the at least two strobe signal lines such that the devices do not share any of the N data signal lines and such that the devices do not share any of the strobe signal lines. The memory system further includes a controller 45 to communicate in parallel with the first and second memory devices through the N data signal lines and the at least two strobe signal lines.

Abstract: A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit comprises an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.

Abstract: A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.

Abstract: A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations. Each of the read operations performs a read of pre-specified data stored in at least one memory component while using different ones of delayed enable signals. Data read from respective dummy read operations is compared to identify successful read operations while the timing information from successful read operations is compared to identify a suitable delayed enable signal.