Patents by Inventor Jae Baik
Jae Baik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923145Abstract: A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are stacked in a first direction and a plurality of internal electrodes stacked with the dielectric layer interposed therebetween and external electrodes formed outside the body and connected to the internal electrodes. The body includes an active portion and a side margin portion covering the active portion and opposing each other in a second direction, and 1<A2/M1?1.5 and A2<A1 in which A1 is an average grain size of the dielectric layers in a central region of the active portion, A2 is an average grain size of the dielectric layers at an active boundary part of the active portion adjacent to the side margin portion, and M1 is an average grain size of the dielectric layers in a central region of the side margin portion.Type: GrantFiled: September 2, 2021Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Je Hee Lee, Seung In Baik, Ji Su Hong, Eun Ha Jang, Hyoung Uk Kim, Jae Sung Park
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Patent number: 8923057Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.Type: GrantFiled: December 30, 2010Date of Patent: December 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Myoung Bum Lee, Ki Hyun Hwang, Seung Jae Baik
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Publication number: 20140370255Abstract: This invention relates to a method of producing a coextrusion blown film is described. The method involves coextruding a blown film having 3 to 11 layers, including a first skin layer and a second skin layer, the first skin layer comprising nylon, and the second skin layer having a different melting temperature than the first skin layer. The film is then cooled before being passed through steam. The method can be used to produce a coextrusion blown film that has reduced curling.Type: ApplicationFiled: January 22, 2014Publication date: December 18, 2014Applicant: Alros Products LimitedInventors: Jae BAIK, Elvio Cavicchia
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Patent number: 8460999Abstract: A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.Type: GrantFiled: May 31, 2011Date of Patent: June 11, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jae Baik, Hong-Suk Kim, Si-Young Choi, Ki-Hyun Hwang, Sang-Jin Hyun
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Patent number: 8405137Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.Type: GrantFiled: November 21, 2011Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Zong-Liang Huo, Seung-Jae Baik, In-Seok Yeo, Hong-Sik Yoon, Shi-Eun Kim
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Patent number: 8377434Abstract: The present invention relates to a cosmetic composition containing enzymes, and more particularly to a cosmetic composition, which contains, as active ingredients, 1) papain, and 2) at least one selected from the group consisting of theanine and N-acetyl glucosamine, and thus functions to control the skin turnover cycle and promote the exfoliation of skin keratin.Type: GrantFiled: November 28, 2006Date of Patent: February 19, 2013Assignee: Amorepacific CorporationInventors: Seung Jae Baik, Beung Young Kang, Eun Joo Kim
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Publication number: 20120061752Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Inventors: Zong-Liang Huo, Seung-Jae Baik, In-Seok Yeo, Hong-Sik Yoon, Shi-Eun Kim
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Patent number: 8114735Abstract: In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.Type: GrantFiled: September 20, 2007Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Suk Kim, Si-Young Choi, Ki-Hyun Hwang, Han-Mei Choi, Seung-Hwan Lee, Seung-Jae Baik, Sun-Jung Kim, Kwang-Min Park, In-Sun Yi
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Patent number: 8084316Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.Type: GrantFiled: May 1, 2006Date of Patent: December 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Zong-Liang Huo, Seung-Jae Baik, In-Seok Yeo, Hong-Sik Yoon, Shi-Eun Kim
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Publication number: 20110237059Abstract: A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.Type: ApplicationFiled: May 31, 2011Publication date: September 29, 2011Inventors: Seung-Jae Baik, Hong-Suk Kim, Si-Young Choi, Ki-Hyun Hwang, Sang-Jin Hyun
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Publication number: 20110237055Abstract: A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.Type: ApplicationFiled: March 22, 2011Publication date: September 29, 2011Inventors: Yong-hoon Son, Si-Young Choi, Myoung-Bum Lee, Ki-Hyun Hwang, Seung-Jae Baik, Jeong Hee Han
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Publication number: 20110199804Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.Type: ApplicationFiled: December 30, 2010Publication date: August 18, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hoon SON, Myoung Bum LEE, Ki Hyun HWANG, Seung Jae BAIK
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Patent number: 7973355Abstract: A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.Type: GrantFiled: July 14, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jae Baik, Hong-Suk Kim, Si-Young Choi, Ki-Hyun Hwang, Sang-Jin Hyun
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Publication number: 20100254969Abstract: The present invention relates to a cosmetic composition containing enzymes, and more particularly to a cosmetic composition, which contains, as active ingredients, 1) papain, and 2) at least one selected from the group consisting of theanine and N-acetyl glucosamine, and thus functions to control the skin turnover cycle and promote the exfoliation of skin keratin.Type: ApplicationFiled: November 28, 2006Publication date: October 7, 2010Applicant: Amorepacific CorporationInventors: Seung Jae Baik, Beung Young Kang, Eun Joo Kim
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Patent number: 7795659Abstract: In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.Type: GrantFiled: May 1, 2008Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sik Yoon, In-Seok Yeo, Seung-Jae Baik, Zong-Liang Huo, Shi-Eun Kim
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Patent number: 7791130Abstract: Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a second direction which intersects the first direction; word lines extending in the first direction and covering the active region; and charge storage patterns between the word lines and active region, wherein the charge storage patterns may be in pairs on both edges of the bit lines, and a pair of charge storage patterns may be spaced apart from each other by the word lines.Type: GrantFiled: August 12, 2008Date of Patent: September 7, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jae Baik, Si-Young Choi, Ki-Hyun Hwang
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Patent number: 7566615Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.Type: GrantFiled: March 9, 2006Date of Patent: July 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Seung-Jae Baik
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Publication number: 20090134451Abstract: An example embodiment of a non-volatile memory device and an example embodiment of a method of fabricating the same are provided. The non-volatile memory devices includes a tunnel insulation layer on a semiconductor substrate, a charge storage layer on the tunnel insulation layer, a blocking insulation layer including at least one nano dot on the charge storage layer, and a control gate electrode on the blocking insulation layer.Type: ApplicationFiled: November 20, 2008Publication date: May 28, 2009Inventors: Seung-Jae Baik, Jin-Tae Noh, Hong-Suk Kim, In-Sun Yi, Si-Young Choi, Ki-Hyun Hwang
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Publication number: 20090114904Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described.Type: ApplicationFiled: December 31, 2008Publication date: May 7, 2009Inventors: Seung-Jae Baik, In-Seok Yeo, Sang-Sig Kim, Ki-Hyun Kim, Dong-Young Jeong
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Publication number: 20090045448Abstract: Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a second direction which intersects the first direction; word lines extending in the first direction and covering the active region; and charge storage patterns between the word lines and active region, wherein the charge storage patterns may be in pairs on both edges of the bit lines, and a pair of charge storage patterns may be spaced apart from each other by the word lines.Type: ApplicationFiled: August 12, 2008Publication date: February 19, 2009Inventors: Seung-Jae Baik, Si-Young Choi, Ki-Hyun Hwang