Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: Disclosed herein is a focal length adjustment apparatus in which a magnetic fluid that serves as attenuation means is injected between a magnet and a coil to achieve an improvement in a magnetic flux density and damping effect. The apparatus comprises a moving unit including a lens barrel that contains at least one lens therein, and a coil arranged on an outer circumference of the lens barrel, a fixed unit including a yoke formed with an opening for receiving the lens barrel, a case into which the yoke is inserted and mounted, and a magnet affixed to the yoke to be arranged adjacent to the coil, a supporting member used to elastically support the moving unit relative to the case, and attenuation means interposed between the coil and the magnet to attenuate vibration of the moving unit.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.

Abstract: There are provided highly integrated semiconductor memory devices being suitable for storing two bits of data in one unit cell, and methods of fabricating the same. The unit cell of the semiconductor memory device includes a semiconductor substrate and source and drain regions formed in the semiconductor substrate and spaced from each other. First and second data lines are formed to run across over a channel region between the source and drain regions and to be disposed adjacent to the source and drain regions respectively. A first MTJ barrier layer pattern is disposed between the first data line and the channel region. A second MTJ barrier layer pattern is disposed between the second data line and the channel region. A first floated storage node is disposed between the first MTJ barrier layer pattern and the channel region. A second floated storage node is disposed between the second MTJ barrier layer pattern and the channel region.

Abstract: A nonvolatile semiconductor memory device includes a substrate having a trench therein, a gate electrode in the trench, and a plurality of source/drain regions in the substrate adjacent the gate electrode. A pair of channel regions extends along sidewalls of the trench between respective pairs of adjacent source/drain regions. A charge trapping layer is between the gate electrode and the channel regions, and an insulation layer is between the charge trapping layer and the channel regions. Methods of forming nonvolatile semiconductor memory devices include forming a recess in a substrate, forming a first source/drain region beneath the recess, and forming a second source/drain region and a third source/drain region at an upper portion of the substrate on opposing sides of the recess and spaced apart from the first source/drain region. An insulation structure in the recess includes first and second insulation layers and a charge trapping layer between the first and the second insulation layers.

Abstract: A scalable two-transistor memory (STTM) device includes a planar transistor and a vertical transistor on a semiconductor substrate. The planar transistor includes spaced apart metal silicide source/drain regions on the substrate and a floating gate electrode on the substrate between the metal silicide source/drain regions that controls a channel region of the planar transistor. The vertical transistor includes a tunnel junction structure on the floating gate electrode and a control gate electrode on a sidewall of the tunnel junction structure that controls a channel region of the vertical transistor. Related methods of forming STTM devices are also discussed.

Abstract: A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.