Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.

Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.

Abstract: A semiconductor apparatus may include a capacitance measuring circuit. The capacitance measuring circuit may include a constant current circuit configured to output a constant current. The capacitance measuring circuit may include a voltage converting circuit configured to convert the constant current into a detection voltage, and compensate for a variation of the detection voltage due to internal leakage current of the voltage converting circuit. The capacitance measuring circuit may include a code generating circuit configured to generate a value obtained by detecting a time elapsed while the detection voltage increases to a reference voltage, as a code signal.

Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.

Abstract: A semiconductor device may include a trimming circuit suitable for generating a reference voltage that is adjusted based on a code value, and an internal voltage generation circuit suitable for generating an internal voltage based on the reference voltage, wherein the internal voltage generation circuit is suitable for dividing the internal voltage in a division ratio that varies depending on an operation mode and for generating the internal voltage based on comparison of the divided internal voltage with the reference voltage.

Abstract: A semiconductor device may include a trimming circuit suitable for generating a reference voltage that is adjusted based on a code value, and an internal voltage generation circuit suitable for generating an internal voltage based on the reference voltage, wherein the internal voltage generation circuit is suitable for dividing the internal voltage in a division ratio that varies depending on an operation mode and for generating the internal voltage based on comparison of the divided internal voltage with the reference voltage.

Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.

Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.

Abstract: A test mode setting circuit may include: a first test mode signal generation unit operated by a first supply voltage, and suitable for activating a first test mode signal at a first voltage level in a state where mode setting is being performed, the first test mode signal corresponding to a test code among a plurality of first test mode signals; and a second test mode signal generation unit operated by a second supply voltage, and suitable for latching the first test mode signal at a second voltage level and generating the latched first test mode signal as a second test mode signal even when the first supply voltage is deactivated to a third supply voltage lower than the first supply voltage.

Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.

Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.

Abstract: A test mode setting circuit may include: a first test mode signal generation unit operated by a first supply voltage, the first test mode signal generation unit suitable for activating a first test mode signal at a first voltage level in a state where mode setting is completed, the first test mode signal corresponding to a test code among a plurality of first test mode signals; and a second test mode signal generation unit operated by a second supply voltage, the second test mode signal generation unit suitable for latching the first test mode signal at a second voltage level and generating the latched first test mode signal as a second test mode signal when a first supply voltage is reset.

Abstract: A differential amplification circuit includes a first current control unit configured to control driving current in response to a voltage level difference between first input voltage and second input voltage, a second current control unit configured to control the driving current in response to a voltage level difference between the second input voltage independent from temperature and a temperature voltage depending on the temperature, and a signal output unit configured to generate a detection signal in response to the driving current.

Abstract: A semiconductor memory device includes a voltage generation unit suitable for selecting one of the voltages which are supplied to a first and a second source voltage terminals, as a source voltage based on a driving mode signal, and generating a bit line precharge voltage by dividing the source voltage according to a resistance ratio determined based on the driving mode signal; a sense amplifier driving unit suitable for receiving the bit line precharge voltage based on a bit line precharge signal and a sense amplifier control signal, and providing a driving voltage through a pull-up power line and a pull-down power line; and a bit line sense amplifier suitable for sensing and amplifying data of a bit line pair by using the driving voltage supplied through the pull-up power line and the pull-down power line.

Abstract: A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.

Abstract: A differential amplification circuit includes a first current control unit configured to control driving current in response to a voltage level difference between first input voltage and second input voltage, a second current control unit configured to control the driving current in response to a voltage level difference between the second input voltage independent from temperature and a temperature voltage depending on the temperature, and a signal output unit configured to generate a detection signal in response to the driving current.

Abstract: An internal voltage control circuit according to an embodiment may include a source power supply selection unit configured to receive a first internal power supply voltage and a second internal power supply voltage and selecting the first internal power supply voltage and the second internal power supply voltage as a source voltage in response to a test mode enable signal, a first reference voltage generation unit configured to receive the source voltage from the source power supply selection unit, and configured to generate a to first low reference voltage and a first high reference voltage. The reference voltage control circuit may also include a second reference voltage generation unit configured to receive the first internal power supply voltage and configured to generate a second low reference voltage and a second high reference voltage.

Abstract: A differential amplification circuit includes a first current control unit configured to control driving current in response to a voltage level difference between first input voltage and second input voltage, a second current control unit configured to control the driving current in response to a voltage level difference between the second input voltage independent from temperature and a temperature voltage depending on the temperature, and a signal output unit configured to generate a detection signal in response to the driving current.

Abstract: An internal voltage control circuit according to an embodiment may include a source power supply selection unit configured to receive a first internal power supply voltage and a second internal power supply voltage and selecting the first internal power supply voltage and the second internal power supply voltage as a source voltage in response to a test mode enable signal, a first reference voltage generation unit configured to receive the source voltage from the source power supply selection unit, and configured to generate a to first low reference voltage and a first high reference voltage. The reference voltage control circuit may also include a second reference voltage generation unit configured to receive the first internal power supply voltage and configured to generate a second low reference voltage and a second high reference voltage.

Abstract: A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.