Abstract: A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value.

Abstract: A semiconductor device includes a reference current generator suitable for generating a reference current, a current-voltage converter suitable for generating a first reference voltage and a second reference voltage in response to the reference current, and an analog-digital converter suitable for generating a digital code value based on a voltage difference between the first and second reference voltages, wherein the reference current generator includes a current control unit for controlling the reference current in response to the digital code value.

Abstract: A semiconductor memory apparatus according to the embodiment includes: an external connection terminal configured to supply an external voltage; a fuse unit configured to perform a fuse rupture operation; and an interruption circuit unit configured to respond to a test signal to determine whether the external connection terminal is connected to the fuse unit.

Abstract: A semiconductor memory apparatus according to the embodiment includes: an external connection terminal configured to supply an external voltage; a fuse unit configured to perform a fuse rupture operation; and an interruption circuit unit configured to respond to a test signal to determine whether the external connection terminal is connected to the fuse unit.

Abstract: A differential amplification circuit includes a first current control unit configured to control driving current in response to a voltage level difference between first input voltage and second input voltage, a second current control unit configured to control the driving current in response to a voltage level difference between the second input voltage independent from temperature and a temperature voltage depending on the temperature, and a signal output unit configured to generate a detection signal in response to the driving current.

Abstract: A reference voltage generation circuit includes: a reference voltage generation unit configured to generate a plurality of reference voltages having mutually different temperature characteristics, a switching unit configured to select and output one of the plurality of reference voltages in response to a control signal, a temperature detection unit configured to detect temperature change and to output a temperature detection signal, and a control unit configured to generate the control signal in response to the temperature detection to signal.

Abstract: A semiconductor integrated circuit includes a pre-charge signal generator configured to pre-charge a plurality of oscillation signals to a certain voltage level in a pre-charge mode, wherein the pre-charge signal generator includes: a first storage unit for storing a first pre-charge oscillation signal in response to a reference oscillation signal, a feedback unit for feeding back a second pre-charge oscillation signal, a second storage unit for storing the second pre-charge oscillation signal corresponding to an output signal of the first storage unit in response to the reference oscillation signal, and a pre-charge signal output unit for outputting a pre-charge signal in response to the first pre-charge oscillation signal and the second pre-charge oscillation signal.

Abstract: A voltage generation circuit includes: a first and second rectification circuits; and one or more amplification units connected between the first and second rectification circuits and configured to amplify an output of the first rectification circuit and provide the amplified output to the second rectification circuit. The second rectification circuit generates a reference voltage.

Abstract: A semiconductor integrated circuit includes a pre-charge signal generator configured to pre-charge a plurality of oscillation signals to a certain voltage level in a pre-charge mode, wherein the pre-charge signal generator includes: a first storage unit for storing a first pre-charge oscillation signal in response to a reference oscillation signal, a feedback unit for feeding back a second pre-charge oscillation signal, a second storage unit for storing the second pre-charge oscillation signal corresponding to an output signal of the first storage unit in response to the reference oscillation signal, and a pre-charge signal output unit for outputting a pre-charge signal in response to the first pre-charge oscillation signal and the second pre-charge oscillation signal.

Abstract: A voltage generation circuit includes: a first and second rectification circuits; and one or more amplification units connected between the first and second rectification circuits and configured to amplify an output of the first rectification circuit and provide the amplified output to the second rectification circuit. The second rectification circuit generates a reference voltage.

Abstract: Internal voltage generation circuit including a reference oscillation signal generator for generating a reference oscillation signal according to a comparison result of a pumping voltage with a reference voltage, an oscillation signal generator for generating a plurality of oscillation signals with a predetermined phase difference and a pumping voltage generator for generating a pumping voltage through sequential charge pumping operations performed in response to the plurality of oscillation signals, respectively.

Abstract: A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

Abstract: Test entry circuit and method for generating test entry signal including a first source signal generator configured to receive a test signal through a pad to generate a first mode source signal for a first test mode, a second source signal generator configured to count activation transitions of the test signal to generate a second mode source signal for a second test mode and an entry signal generator configured to receive the first and second mode source signals to generate a first test mode entry signal for entering the first test mode and a second test mode entry signal for entering the second test mode.

Abstract: An internal source voltage generation circuit includes main source voltage driving means configured to drive an internal source voltage terminal to a predetermined voltage level; and additional source voltage driving means configured to additionally drive the internal source voltage terminal in response to a data strobe signal.

Abstract: A back-bias voltage generating circuit controls the back-bias voltage in a predetermined range by detecting the back-bias voltage in case the back-bias voltage level decreases below a predetermined target level. The circuit includes first and second detecting units outputting respective detection signals, which detect a voltage level of the terminal based on respective higher first and lower second target levels. An oscillator generates an oscillation signal that oscillates at a predetermined frequency, in response to a detection signal of the first voltage detecting unit. A charge pumping unit drives the terminal by performing charge pumping in response to the oscillation signal. A voltage level control unit controls the voltage level of the terminal in response to the detection signals, whereby the terminal's voltage level is lower than the first target level and higher than the second target level.

Abstract: A semiconductor memory device includes a voltage detector configured to detect a voltage level of an external power supply voltage, a first core voltage generation driver configured to operate when the external power supply voltage is in a high level region and a second core voltage generation driver configured to operate when the external power supply voltage is in a low level region.

Abstract: Internal voltage generation circuit including a reference oscillation signal generator for generating a reference oscillation signal according to a comparison result of a pumping voltage with a reference voltage, an oscillation signal generator for generating a plurality of oscillation signals with a predetermined phase difference and a pumping voltage generator for generating a pumping voltage through sequential charge pumping operations performed in response to the plurality of oscillation signals, respectively.

Abstract: An internal source voltage generation circuit includes main source voltage driving means configured to drive an internal source voltage terminal to a predetermined voltage level; and additional source voltage driving means configured to additionally drive the internal source voltage terminal in response to a data strobe signal.

Abstract: Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detection circuit to generate a uniform core voltage.

Abstract: Internal voltage generation circuit including a reference oscillation signal generator for generating a reference oscillation signal according to a comparison result of a pumping voltage with a reference voltage, an oscillation signal generator for generating a plurality of oscillation signals with a predetermined phase difference and a pumping voltage generator for generating a pumping voltage through sequential charge pumping operations performed in response to the plurality of oscillation signals, respectively.