Patents by Inventor Jae Ean Lee
Jae Ean Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11699643Abstract: A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.Type: GrantFiled: January 29, 2021Date of Patent: July 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ik Jun Choi, Jae Ean Lee, Kwang Ok Jeong, Young Gwan Ko, Jung Soo Byun
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Publication number: 20230134541Abstract: A semiconductor package is provided.Type: ApplicationFiled: June 9, 2022Publication date: May 4, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Ean LEE, Gyu Jin CHOI
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Publication number: 20220384324Abstract: Disclosed is a semiconductor package device comprising a semiconductor chip including first and second chip pads on an active surface of the semiconductor chip, and a redistribution substrate on the first and second chip pads. The redistribution substrate includes first and second redistribution patterns sequentially stacked on the active surface. The first redistribution pattern includes a first via part and a first via pad part vertically overlapping the first via part. The second redistribution pattern includes a second via part and a second via pad part vertically overlapping the second via part. The first via part contacts the first chip pad. The second via part contacts the second chip pad. A length of the second via part is greater than that of the first via part.Type: ApplicationFiled: January 4, 2022Publication date: December 1, 2022Inventors: Gyujin Choi, Jae-Ean Lee, Changeun Joo
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Patent number: 11189552Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.Type: GrantFiled: May 5, 2020Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ean Lee, Tae Sung Jeong, Young Gwan Ko, Suk Ho Lee, Jung Soo Byun
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Publication number: 20210151370Abstract: A method for manufacturing a semiconductor package includes disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate, forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate, embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole, forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure, and forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.Type: ApplicationFiled: January 29, 2021Publication date: May 20, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ik Jun CHOI, Jae Ean LEE, Kwang Ok JEONG, Young Gwan KO, Jung Soo BYUN
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Patent number: 10916495Abstract: A semiconductor package includes a supporting member that has a cavity and includes a wiring structure connecting first and second surfaces opposing each other. A connection member is on the second surface of the supporting member and includes a first redistribution layer connected to the wiring structure. A semiconductor chip is on the connection member in the cavity and has connection pads connected to the first redistribution layer. An encapsulant encapsulates the semiconductor chip disposed in the cavity and covers the first surface of the supporting member. A second redistribution layer includes wiring patterns embedded in the encapsulant and has exposed surfaces and connection vias that penetrate through the encapsulant to connect the wiring structure and the wiring patterns to each other.Type: GrantFiled: March 26, 2018Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ik Jun Choi, Jae Ean Lee, Kwang Ok Jeong, Young Gwan Ko, Jung Soo Byun
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Patent number: 10796997Abstract: A semiconductor package including an organic interposer includes: a semiconductor chip; a connection member on the semiconductor chip and including a pad layer, a redistribution layer, and an insulating layer; a bonding member between the semiconductor chip and the pad layer; a surface treatment layer on the pad layer and including at least one metal layer; and an under-bump metallurgy (UBM) layer embedded in the connection member. The UBM layer includes a UBM pad, at least one plating layer on the UBM pad, and a UBM via. The surface treatment layer is disposed only on one surface of the pad layer, the plating layer are is disposed only on one surface of the UBM pad, and at least a portion of a side surface of the plating layer is spaced apart from a side surface of the insulating layer surrounding the plating layer.Type: GrantFiled: November 29, 2018Date of Patent: October 6, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ean Lee, Han Na Jin, Tae Sung Jeong, Young Gwan Ko, Jung Soo Byun
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Patent number: 10790224Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.Type: GrantFiled: April 30, 2019Date of Patent: September 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ean Lee, Tae Sung Jeong, Young Gwan Ko, Ik Jun Choi, Jung Soo Byun
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Publication number: 20200266137Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ean LEE, Tae Sung JEONG, Young Gwan KO, Suk Ho LEE, Jung Soo BYUN
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Patent number: 10665535Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.Type: GrantFiled: March 6, 2018Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ean Lee, Tae Sung Jeong, Young Gwan Ko, Suk Ho Lee, Jung Soo Byun
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Patent number: 10636743Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.Type: GrantFiled: April 4, 2019Date of Patent: April 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ho Baek, Sang Kun Kim, Ye Jeong Kim, Jae Ean Lee, Jae Hoon Choi
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Publication number: 20200066639Abstract: A semiconductor package including an organic interposer includes: a semiconductor chip; a connection member on the semiconductor chip and including a pad layer, a redistribution layer, and an insulating layer; a bonding member between the semiconductor chip and the pad layer; a surface treatment layer on the pad layer and including at least one metal layer; and an under-bump metallurgy (UBM) layer embedded in the connection member. The UBM layer includes a UBM pad, at least one plating layer on the UBM pad, and a UBM via. The surface treatment layer is disposed only on one surface of the pad layer, the plating layer are is disposed only on one surface of the UBM pad, and at least a portion of a side surface of the plating layer is spaced apart from a side surface of the insulating layer surrounding the plating layer.Type: ApplicationFiled: November 29, 2018Publication date: February 27, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ean LEE, Han Na JIN, Tae Sung JEONG, Young Gwan KO, Jung Soo BYUN
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Patent number: 10438884Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.Type: GrantFiled: March 13, 2018Date of Patent: October 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Ean Lee, Tae Sung Jeong, Young Gwan Ko, Ik Jun Choi, Jung Soo Byun
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Publication number: 20190259697Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Inventors: Jae Ean LEE, Tae Sung JEONG, Young Gwan KO, Ik Jun CHOI, Jung Soo BYUN
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Publication number: 20190229060Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.Type: ApplicationFiled: April 4, 2019Publication date: July 25, 2019Inventors: Yong Ho BAEK, Sang Kun KIM, Ye Jeong KIM, Jae Ean LEE, Jae Hoon CHOI
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Publication number: 20190229070Abstract: A fan-out semiconductor package includes: a semiconductor chip; a redistribution portion disposed below the semiconductor chip; a reinforcing member disposed on the redistribution portion and surrounding the semiconductor chip; and an encapsulant disposed on the redistribution portion to embed the semiconductor chip and the reinforcing member therein.Type: ApplicationFiled: August 20, 2018Publication date: July 25, 2019Inventors: Yi Eok KWON, Jae Ean LEE, Hak Young LEE
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Patent number: 10325856Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.Type: GrantFiled: December 20, 2016Date of Patent: June 18, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yong Ho Baek, Sang Kun Kim, Ye Jeong Kim, Jae Ean Lee, Jae Hoon Choi
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Publication number: 20190164876Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.Type: ApplicationFiled: March 13, 2018Publication date: May 30, 2019Inventors: Jae Ean LEE, Tae Sung JEONG, Young Gwan KO, Ik Jun CHOI, Jung Soo BYUN
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Patent number: 10306778Abstract: A printed circuit board includes a first substrate including a first insulation layer and a first circuit layer including a bonding pad, the bonding pad disposed on the first insulation layer, a second substrate disposed on the first substrate and having a cavity exposing the bonding pad to an outside, and a dam disposed between the bonding pad and an inner wall of the cavity.Type: GrantFiled: February 11, 2016Date of Patent: May 28, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jae-Ean Lee, Jee-Soo Mok, Young-Gwan Ko, Soon-Oh Jung, Kyung-Hwan Ko, Yong-Ho Baek
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Patent number: 10297553Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.Type: GrantFiled: May 17, 2018Date of Patent: May 21, 2019Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yong Ho Baek, Sang Kun Kim, Ye Jeong Kim, Jae Ean Lee, Jae Hoon Choi