Patents by Inventor Jae-eun Park
Jae-eun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8623714Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.Type: GrantFiled: March 22, 2010Date of Patent: January 7, 2014Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd.Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee
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Patent number: 8563394Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.Type: GrantFiled: April 11, 2011Date of Patent: October 22, 2013Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.Inventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
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Patent number: 8298897Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: GrantFiled: March 23, 2012Date of Patent: October 30, 2012Assignees: International Business Machines Corporation, Globalfoundries Inc.Inventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Publication number: 20120256268Abstract: Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.Type: ApplicationFiled: April 11, 2011Publication date: October 11, 2012Applicants: GlobalFoundries, Inc., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Weipeng Li, Deleep R. Nair, Jae-Eun Park, Voon-Yew Thean, Young Way Teh
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Patent number: 8237197Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: GrantFiled: July 7, 2010Date of Patent: August 7, 2012Assignees: International Business Machines Corporation, Globalfoundries Inc.Inventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Publication number: 20120190160Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: ApplicationFiled: March 23, 2012Publication date: July 26, 2012Applicants: GLOBALFOUNDRIES Inc., International Business Machines CorporationInventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Patent number: 8120058Abstract: A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.Type: GrantFiled: October 28, 2009Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Jae-Eun Park, Xinlin Wang, Xiangdong Chen
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Publication number: 20120007145Abstract: A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.Type: ApplicationFiled: July 7, 2010Publication date: January 12, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Jie Deng, Weipeng Li, Deleep R. Nair, Jae-Eun Park, Daniel Tekleab, Xiaobin Yuan, Nam Sung Kim
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Publication number: 20110227136Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD., CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Jae-Eun Park, Weipeng Li, Deleep R. Nair, M. Dean Sciacca, Voon-Yew Thean, Ava Wan, Dong-Hun Lee, Yong-Meng Lee
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Patent number: 7989922Abstract: An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.Type: GrantFiled: February 8, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Randy W. Mann, Jae-Eun Park, Richard A. Wachnik
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Patent number: 7939894Abstract: The present invention provides a method of controlling bias in an electrical device including providing semiconductor devices on a bulk semiconductor substrate each including an active body region that is isolated from the active body region of adjacent devices, and providing a body resistor in electrical contact with the active body region of the bulk semiconductor substrate, wherein the body resistor provides for adjustability of the body potential of the semiconductor devices. In another aspect the present invention provides a semiconductor device including a bulk semiconductor substrate, at least one field effect transistor formed on the bulk semiconductor substrate including an isolated active body region, and a resistor in electrical communication with the isolated active body region.Type: GrantFiled: August 4, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Terence B. Hook, Jenny Hu, Jae-Eun Park
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Publication number: 20110095333Abstract: A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.Type: ApplicationFiled: October 28, 2009Publication date: April 28, 2011Applicant: International Business Machines CorporationInventors: Jae-Eun Park, Xinlin Wang, Xiangdong Chen
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Publication number: 20110082680Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.Type: ApplicationFiled: October 6, 2009Publication date: April 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Anda C. Mocuta, Jae-Eun Park, Kern Rim, Xiaojun Yu
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Patent number: 7651729Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.Type: GrantFiled: May 12, 2005Date of Patent: January 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seok Kim, Jong-Pyo Kim, Ha-Jin Lim, Jae-Eun Park, Hyung-Suk Jung, Jong-Ho Lee, Jong-Ho Yang
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Patent number: 7615432Abstract: A stress nitride structure is formed on an integrated circuit field effect transistor by high density plasma (HDP) depositing a first stress nitride layer on the integrated circuit field effect transistor and then plasma enhanced chemical vapor depositing (PECVD) a second stress nitride layer on the first stress nitride layer. The first stress nitride layer is non-conformal and the second stress nitride layer is conformal. Related structures also are described.Type: GrantFiled: November 2, 2005Date of Patent: November 10, 2009Assignees: Samsung Electronics Co., Ltd., International Business Machines CorporationInventors: Junjung Kim, Jae-eun Park, Ja-hum Ku, Daewon Yang
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Patent number: 7612414Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.Type: GrantFiled: March 29, 2007Date of Patent: November 3, 2009Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd.Inventors: Xiangdong Chen, Jun Jung Kim, Young Gun Ko, Jae-Eun Park, Haining S. Yang
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Publication number: 20090200642Abstract: An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.Type: ApplicationFiled: February 8, 2008Publication date: August 13, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Randy W. Mann, Jae-Eun Park, Richard Andre Wachnik
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Patent number: 7521308Abstract: A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.Type: GrantFiled: December 26, 2006Date of Patent: April 21, 2009Assignee: International Business Machines CorporationInventors: Deleep R. Nair, Christopher V. Baiocco, Xiangdong Chen, Junjung Kim, Jae-eun Park, Daewon Yang
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Patent number: 7510969Abstract: In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.Type: GrantFiled: January 9, 2007Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-won Lee, Kang-soo Chu, Jae-eun Park, Jong-ho Yang
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Publication number: 20090014807Abstract: Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for inducing a second stress. An interface between the first and second stress portions is self-aligned and co-planar. To produce a co-planar self-aligned interface, polishing, for example, mechanical chemical polishing is used.Type: ApplicationFiled: July 13, 2007Publication date: January 15, 2009Applicants: Chartered Semiconductor Manufacturing, Ltd., Samsung Electronics Co., Ltd, International Business Machines Corporation, Infineon Technologies AGInventors: Teck Jung TANG, Dae Kwon Kang, Sunfei Fang, Tae Hoon Lee, Scott D. Allen, Fang Chen, Frank Huebinger, Jun Jung Kim, Jae Eun Park