Abstract: Provided is an operation method for a digital hologram implementation device including a backlight and a spatial light modulator, the operation method including setting an initial phase value of an optical signal to a remedy phase, computing a reduced phase based on the remedy phase, correcting the remedy phase based on a difference between the reduced phase and a preset optimized phase, determining whether the corrected remedy phase is a stabilized phase, performing forward propagation on the stabilized phase and an amplitude of the optical signal, correcting the amplitude of the optical signal, performing backward propagation on the corrected amplitude and the stabilized phase, and determining whether a phase derived by the backward propagation is an optimized phase.

Abstract: Provided is a method for manufacturing a vertical channel thin film transistor. The method for manufacturing the vertical channel thin film transistor includes forming a bottom source drain electrode, forming a first interlayer insulating layer, forming first middle source drain electrodes, forming a second interlayer insulating layer, forming a top source drain electrode, forming an opening through which portions of the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode are exposed, forming channel layers, forming a gate insulating layer on the channel layers, the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode, and forming gate electrodes on the gate insulating layer.

Abstract: A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.

Abstract: An apparatus which analyses a depth of a holographic image is provided. The apparatus includes an acquisition unit that acquires a hologram, a restoration unit that restores a three-dimensional holographic image by irradiating the hologram with a light source, an image sensing unit that senses a depth information image of the restored holographic image, and an analysis display unit that analyzes a depth quality of the holographic image, based on the sensed depth information image, and the image sensing unit uses a lensless type of photosensor.

Abstract: A complementary thin film transistor (TFT) includes a substrate and a first TFT and a second TFT disposed on the substrate, wherein a first conductive semiconductor layer of the first TFT and a second gate electrode layer of the second TFT are disposed in the same layer and include the same material.

Abstract: Provided is a static random-access memory (SRAM) device.

Abstract: Provided are a semiconductor device, a display panel, and a display device including the same. The semiconductor device includes a lower electrode on one side of a substrate, a spacer on another side of the substrate, a middle electrode on the spacer, a lower channel layer on portions of a sidewall of the spacer, the middle electrode, and the lower electrode, a lower gate insulating layer on the lower channel layer, a common gate electrode on the gate insulating layer, an upper gate insulating layer on the common gate electrode, an upper electrode on the spacer and the upper gate insulating layer of the middle electrode, an upper channel layer connected to the upper electrode and disposed on a sidewall of the upper gate insulating layer, and a contact electrode connected to a portion of the upper channel layer and passing through the lower gate insulating layer and the upper gate insulating layer outside the common gate electrode so as to be connected to the lower electrode.

Abstract: Provided is a stretchable display device. The stretchable display device includes a substrate and a base pattern on the substrate, wherein the base pattern comprises a first portion, a second portion, and a connection portion configured to connect the first portion to the second portion. The stretchable display device includes a lower electrode on the first portion of the base pattern; an upper electrode on the lower electrode, a light emitting structure between the lower electrode and the upper electrode, and a protective layer configured to cover top and side surfaces of the upper electrode, side surfaces of the light emitting structure, a side surface of the lower electrode, and a portion of a side surface of the base pattern. The upper electrode extends to a top surface of the connection portion and a top surface of the second portion of the base pattern, and the first portion and the second portion of the base pattern extend in a first direction parallel to a top surface of the substrate.

Abstract: Provided is a static random-access memory (SRAM) device.

Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

Abstract: Provided are stretchable electronics and a method for manufacturing the same. The stretchable electronics may include a substrate, a plurality of electronic elements disposed to be spaced apart from each other on the substrate, and a wire structure disposed on the substrate to connect the plurality of electronic elements to each other. The wire structure may include an insulator extending from one of the electronic elements to the other of the adjacent electronic elements and a metal wire configured to cover a top surface and side surfaces of the insulator. The insulator may include at least one bent part in a plan view.

Abstract: Provided are a semiconductor device, a display panel, and a display device including the same. The semiconductor device includes a lower electrode on one side of a substrate, a spacer on another side of the substrate, a middle electrode on the spacer, a lower channel layer on portions of a sidewall of the spacer, the middle electrode, and the lower electrode, a lower gate insulating layer on the lower channel layer, a common gate electrode on the gate insulating layer, an upper gate insulating layer on the common gate electrode, an upper electrode on the spacer and the upper gate insulating layer of the middle electrode, an upper channel layer connected to the upper electrode and disposed on a sidewall of the upper gate insulating layer, and a contact electrode connected to a portion of the upper channel layer and passing through the lower gate insulating layer and the upper gate insulating layer outside the common gate electrode so as to be connected to the lower electrode.

Abstract: Disclosed are a biometric device and a biometric system including the same. The device includes a biogenic-synthesized film, a reflective layer disposed on one side of the biogenic-synthesized film, a light source disposed on the reflective layer to generate light, a beam splitter disposed between the light source and the reflective layer to provide the light to the reflective layer and another side of the biogenic-synthesized film, and a light switching layer disposed between the beam splitter and the reflective layer to switch the light provided to the reflective layer.

Abstract: Provided is a pressure sensitive display device including a sensing substrate, a reaction substrate provided on the sensing substrate, and spacers provided between the sensing substrate and the reaction substrate to space the sensing substrate apart from the reaction substrate. Here, the sensing substrate includes a flexible substrate and a touch electrode provided on one surface of the flexible substrate, which faces the reaction substrate. The reaction substrate includes a transparent substrate, a transparent electrode provided on one surface of the transparent substrate, which faces the sensing substrate, and a light emitting layer disposed on the transparent electrode.

Abstract: A hologram display device includes a light source unit that emits light, a spatial light modulator that modulates the light emitted from the light source unit, and a random pinhole panel. The random pinhole panel includes a plurality of pinholes of a random position or a random size and is arranged in line with an output part of the spatial light modulator. In the hologram display device and the method of manufacturing the hologram display device, a position and size of a random pinhole on the random pinhole are not limited to inside each pixel of the spatial light modulator.

Abstract: A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.

Abstract: Disclosed is an apparatus of analyzing a depth of a holographic image according to the present disclosure, which includes an acquisition unit that acquires a hologram, a restoration unit that restores a three-dimensional holographic image by irradiating the hologram with a light source, an image sensing unit that senses a depth information image of the restored holographic image, and an analysis display unit that analyzes a depth quality of the holographic image, based on the sensed depth information image, and the image sensing unit uses a lensless type of photosensor.

Abstract: Provided is an operation method for a digital hologram implementation device including a backlight and a spatial light modulator, the operation method including setting an initial phase value of an optical signal to a remedy phase, computing a reduced phase based on the remedy phase, correcting the remedy phase based on a difference between the reduced phase and a preset optimized phase, determining whether the corrected remedy phase is a stabilized phase, performing forward propagation on the stabilized phase and an amplitude of the optical signal, correcting the amplitude of the optical signal, performing backward propagation on the corrected amplitude and the stabilized phase, and determining whether a phase derived by the backward propagation is an optimized phase.

Abstract: Provided are a stretchable electronic device and a method for manufacturing the same. The stretchable electronic device includes lines having lower pads, a chip provided on the lower pads and having first upper pads, which are wider than the lower pads, and an adhesive layer provided outside the lower pads or between the lower pads and bonded to the first upper pads.

Abstract: Disclosed are a biometric device and a biometric system including the same. The device includes a hiogenic-synthesized film, a reflective layer disposed on one side of the biogenic-synthesized film, a light source disposed on the reflective layer to generate light, a beam splitter disposed between the light source and the reflective layer to provide the light to the reflective layer and another side of the biogenic-synthesized film, and a light switching layer disposed between the beam splitter and the reflective layer to switch the light provided to the reflective layer.