Patents by Inventor Jae Eun Pi
Jae Eun Pi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170177922Abstract: Provided is a fingerprint sensor. The fingerprint sensor according to an embodiment of the inventive concept includes a plurality of transmission lines, a plurality of receive lines, and a sensor array including sensor units connected to the plurality of transmission lines. Each of the sensor units includes a switch transistor having a gate terminal and one terminal, which are commonly connected to a corresponding transmission line of the plurality of transmission lines and a sensor transistor connected between the other end of the switch transistor and a corresponding receive line of the plurality of receive lines. The sensor transistor performs a current suppression on in response to a voltage of a virtual gate that is touched by a fingerprint.Type: ApplicationFiled: December 15, 2016Publication date: June 22, 2017Inventor: Jae-Eun PI
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Publication number: 20170176834Abstract: Provided is a light modulating device including a light modulating unit provided on a substrate, a driving unit electrically connected to the light modulating unit and configured to drive the light modulating unit, and a cover disposed on the light modulating unit and configured to seal the light modulating unit, wherein the light modulating unit comprises an electrochromic device.Type: ApplicationFiled: November 16, 2016Publication date: June 22, 2017Inventors: Tae-Youb KIM, Yong Hae KIM, Seong-Mok CHO, Jong-Heon YANG, Jae-Eun PI
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Publication number: 20170178586Abstract: A display apparatus may include: a first base substrate; a driving circuit unit disposed on the first base substrate and including a plurality of gate lines, a plurality of data lines and a plurality of thin film transistors electrically connected to the plurality of gate lines and the plurality of data lines; a driving circuit controller including a gate driver disposed between the driving circuit unit and the first base substrate and outputting a gate signal to the gate lines, a data driver outputting a data voltage to the plurality of data lines and an interface circuit unit controlling operation timings of the gate driver and the data driver; and an image embodying unit disposed on the driving circuit unit and embodying an image in response to a signal received from the driving circuit unit.Type: ApplicationFiled: July 29, 2016Publication date: June 22, 2017Inventors: Tae-Youb KIM, Chunwon BYUN, Chi-Sun HWANG, Yong Hae KIM, Jae-Eun PI, Hojun RYU, Seong-Mok CHO
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Patent number: 9628079Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.Type: GrantFiled: February 22, 2016Date of Patent: April 18, 2017Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Jae-Eun Pi, Chunwon Byun, OhSang Kwon, Eunsuk Park, Min Ki Ryu, Chi-Sun Hwang
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Publication number: 20160267827Abstract: A display panel includes pixels connected to each of gate lines and data lines. Each of the pixels includes a first transistor connected between a corresponding data line among the data lines and a first node and configured to deliver a data signal of the corresponding data line to the first node in response to an input signal received through a corresponding gate line among the gate lines, a reflective element circuit connected to the first node, and configured to implement the reflective mode in response to a signal of the first node when a first mode selection signal indicates a reflective mode, an emissive element circuit connected to a second node, and configured to implement the emissive mode in response to the signal of the first node when the mode selection mode indicates an emissive mode.Type: ApplicationFiled: January 27, 2016Publication date: September 15, 2016Inventors: Chunwon BYUN, Jae-Eun PI, Kyoung Ik CHO, Hye Yong CHU, Chi-Sun HWANG
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Publication number: 20160248426Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.Type: ApplicationFiled: February 22, 2016Publication date: August 25, 2016Inventors: Jae-Eun PI, Chunwon BYUN, OhSang KWON, Eunsuk PARK, Min Ki RYU, Chi-Sun HWANG
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Publication number: 20160240563Abstract: Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern.Type: ApplicationFiled: February 12, 2016Publication date: August 18, 2016Inventors: Sang-Hee PARK, Chi-Sun HWANG, Min Ki RYU, Jae-Eun PI, Jong-Beom KO, Hyein YEOM
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Publication number: 20160209809Abstract: Provided is a holographic display device. The holographic display device includes a light source unit configured to emit a light, and a spatial light modulator (SLM) configured to modulate at least one of a phase and amplitude of the light emitted from the light source unit to output a hologram image, and including a plurality of pixel groups that are arranged in a first direction, wherein each of the plurality of pixel groups includes: first pixels arranged in a matrix x1×y1 and providing an image having a first wavelength, and second pixels adjacent to the first pixels in the first direction, arranged in a matrix x2×y2, and providing an image having a second wavelength that is different from the first wavelength.Type: ApplicationFiled: January 12, 2016Publication date: July 21, 2016Inventors: Yong Hae Kim, Chi-Sun Hwang, Gi Heon Kim, Himchan Oh, Hojun Ryu, Chunwon Byun, Myung Lae Lee, Jae Won Lee, Jae-Eun Pi
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Publication number: 20160209808Abstract: A holographic display apparatus includes a light source unit, a spatial light modulator, and a spatial light modulator control circuit for controlling the spatial light modulator, the spatial light modulator control circuit including a data driving circuit for providing a data voltage to a signal line, a demultiplexer circuit which includes a plurality of switching elements connected to the signal line and sequentially turned on, and transfers the data voltage to a transfer line through a turned-on switching element among the switching elements, and a first element connected between the transfer line and a data line, passing a current flowing from the transfer line to the data line, and blocking a current flowing from the data line to the transfer line.Type: ApplicationFiled: January 15, 2016Publication date: July 21, 2016Inventors: Chunwon BYUN, Jae-Eun PI, Yong Hae KIM, HAKYUN LEE, Chi-Sun HWANG
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Patent number: 9263592Abstract: A transistor includes source/drain electrodes provided on a substrate; a semiconductor oxide layer provided between the source/drain electrodes; a gate electrode facing the semiconductor oxide layer; and a gate insulating layer interposed between the semiconductor oxide layer and the gate electrode, wherein the semiconductor oxide layer has a nano-layered structure including at least one first nano layer comprised of a first material and at least one second nano layer comprised of a second material that are alternatingly stacked one on another to provide at least one interface, and wherein the first material and the second material are different materials that are effective to form an electron transfer channel layer at the interface.Type: GrantFiled: September 6, 2013Date of Patent: February 16, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Su Jae Lee, Chi-Sun Hwang, Hye Yong Chu, Sang Chul Lim, Jae-Eun Pi, Min Ki Ryu
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Patent number: 9236006Abstract: Provided is a display device. The display device includes: a pixel including an emissive element circuit, a reflective element circuit, and a switch transistor selecting one of the emissive element circuit and the reflective element circuit; an illumination sensor generating an illumination information signal according to an illumination of an external light source by detecting the external light source; and a controller generating control signals for driving the pixel according to pixel data, wherein the controller generates a light signal controlling the switch transistor by referencing the illumination information signal.Type: GrantFiled: March 13, 2014Date of Patent: January 12, 2016Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyunkoo Lee, Jae-Eun Pi, Chi-Sun Hwang, Jong-Heon Yang
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Patent number: 9099991Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: GrantFiled: October 9, 2013Date of Patent: August 4, 2015Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.Inventors: Sang Hee Park, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyung Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
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Publication number: 20150171833Abstract: Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.Type: ApplicationFiled: July 18, 2014Publication date: June 18, 2015Applicants: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation CorpInventors: Jae-Eun PI, Sang-Hee PARK, Min Ki RYU, Chi-Sun HWANG, OhSang KWON, Eunsuk PARK, Kee-Chan PARK, YeonKyung KIM
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Patent number: 9035688Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.Type: GrantFiled: August 27, 2013Date of Patent: May 19, 2015Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP.Inventors: Jae-Eun Pi, Kee-Chan Park, Sangyeon Kim, Joondong Kim, Yeon Kyung Kim, HongKyun Lym, Sang-Hee Park, Byoung Gon Yu, Chi-Sun Hwang, Jong Woo Kim, OhSang Kwon, Min Ki Ryu
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Publication number: 20150084995Abstract: Provided is a display device. The display device includes: a pixel including an emissive element circuit, a reflective element circuit, and a switch transistor selecting one of the emissive element circuit and the reflective element circuit; an illumination sensor generating an illumination information signal according to an illumination of an external light source by detecting the external light source; and a controller generating control signals for driving the pixel according to pixel data, wherein the controller generates a light signal controlling the switch transistor by referencing the illumination information signal.Type: ApplicationFiled: March 13, 2014Publication date: March 26, 2015Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyunkoo Lee, Jae-Eun Pi, Chi-Sun Hwang, Jong-Heon Yang
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Publication number: 20140159036Abstract: According to example embodiments of the inventive concept, provided is a transistor with a nano-layered oxide semiconductor layer. The oxide semiconductor layer may include at least one first nano layer and at least one second nano layer that are alternatingly stacked one on another. Here, the first nano layer and the second nano layer may include different materials from each other, and thus, a channel with high electron mobility may be formed at the interface between the first and second nano layers. Accordingly, the transistor can have high reliability.Type: ApplicationFiled: September 6, 2013Publication date: June 12, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Su Jae LEE, Chi-Sun HWANG, Hye Yong CHU, Sang Chul LIM, Jae-Eun PI, Min Ki RYU
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Patent number: 8749300Abstract: Disclosed is a DC voltage conversion circuit of a liquid crystal display apparatus, including: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltages applied to gates of the plurality of thin film transistors by inversion of a clock signal, in which each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto.Type: GrantFiled: October 2, 2012Date of Patent: June 10, 2014Assignees: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp.Inventors: Jae Eun Pi, Kee Chan Park, Hong Kyun Leem, Joon Dong Kim, Youn Kyung Kim, Ji Sun Kim, Byoung Gon Yu, Sang Hee Park, Him Chan Oh, Min Ki Ryu, Chi Sun Hwang
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Patent number: 8710866Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: GrantFiled: October 9, 2013Date of Patent: April 29, 2014Assignees: Electronics and Telecomunications Research Institute, Konkuk University Industrial Cooperation Corp.Inventors: Sang Hee Park, Chi Sun Hwang, Sung Min Yoon, Him Chan Oh, Kee Chan Park, Tao Ren, Hong Kyun Leem, Min Woo Oh, Ji Sun Kim, Jae Eun Pi, Byeong Hoon Kim, Byoung Gon Yu
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Publication number: 20140062572Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.Type: ApplicationFiled: August 27, 2013Publication date: March 6, 2014Applicants: Electronics and Telecommunications Research Institute, Konkuk University Industrial Cooperation Corp.Inventors: Jae-Eun PI, Kee-Chan PARK, Sangyeon KIM, Joondong KIM, Yeon Kyung KIM, HongKyun LYM, Sang-Hee PARK, Byoung Gon YU, Chi-Sun HWANG, Jong Woo KIM, OhSang KWON, Min Ki RYU
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Publication number: 20140035621Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicants: Konkuk University Industrial Cooperation Corp, ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Hee PARK, Chi Sun HWANG, Sung MIN Yoon, Him Chan OH, Kee Chan PARK, Tao REN, Hong Kyun LEEM, Min Woo OH, Ji Sun KIM, Jae Eun PI, Byeong Hoon KIM, Byoung Gon YU