Abstract: A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures.

Abstract: A method of displaying an interface for providing a social networking service (SNS) through an anonymous profile, performed by a user terminal, includes displaying a first list of at least one anonymous chatroom created by a user account for an instant messaging service (IMS) using a first region on a first page in an interface for the IMS, displaying a second list of at least one anonymous profile created to be interlinked with the user account using a first region on a second page in the interface for the IMS, and displaying, in response to an input of selecting any one anonymous profile in the second list, an interface for providing the SNS to through the selected anonymous profile.

Abstract: A ferroelectric memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a first ferroelectric layer disposed on the channel layer, a ferroelectric induction layer disposed on the first ferroelectric layer, the ferroelectric induction layer including an insulator, a second ferroelectric layer disposed on the ferroelectric induction layer, and a gate electrode layer disposed on the second ferroelectric layer.

Abstract: A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.

Abstract: A semiconductor device according to an embodiment includes a first electrode, a dielectric layer structure disposed on the first electrode and having a ferroelectric layer and a non-ferroelectric layer, and a second electrode disposed on the dielectric structure. The ferroelectric layer has positive and negative coercive electric fields having different absolute values. The dielectric structure has a non-ferroelectric property.

Abstract: Disclosed is a method of operating a terminal on which an application for an instant messaging service is installed, the method that displays a first user interface (UI) for switching an input mode in a chatting interface of a chatroom in which a user of the application is participating, based on whether the user is assigned an authority to emphasize a message in the chatroom, switches the input mode from a first mode which is a normal mode to a second mode for emphasizing a message, in response to a user input with respect to the first UI, emphasizes a message input in the second mode for a predetermined period in a predetermined manner, and cancels the emphasizing of the message input in the second mode, when the predetermined time elapses.

Abstract: In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.

Abstract: A vertical memory device according to an aspect includes a substrate, a first gate electrode structure disposed on the substrate and a second gate electrode structure spaced apart from the first gate electrode structure in a first direction substantially perpendicular to the substrate, a channel contact electrode layer disposed between the first gate electrode structure and the second gate electrode structure, and a channel layer extending along the first direction and in contact with the channel contact electrode layers and the first and the second gate electrode structures.

Abstract: A semiconductor device according to an embodiment includes a first electrode, a dielectric layer structure disposed on the first electrode and having a ferroelectric layer and a non-ferroelectric layer, and a second electrode disposed on the dielectric structure. The ferroelectric layer has positive and negative coercive electric fields having different absolute values. The dielectric structure has a non-ferroelectric property.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.

Abstract: A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

Abstract: Disclosed is a method of operating a terminal on which an application for an instant messaging service is installed, the method that displays a first user interface (UI) for switching an input mode in a chatting interface of a chatroom in which a user of the application is participating, based on whether the user is assigned an authority to emphasize a message in the chatroom, switches the input mode from a first mode which is a normal mode to a second mode for emphasizing a message, in response to a user input with respect to the first UI, emphasizes a message input in the second mode for a predetermined period in a predetermined manner, and cancels the emphasizing of the message input in the second mode, when the predetermined time elapses.

Abstract: An electronic apparatus and a booting method thereof are provided. The electronic apparatus includes an inputter configured to receive a power-on command, and a memory configured to store task-processing information of tasks for each booting mode. The electronic apparatus further includes a processor configured to, in response to the reception of the power-on command, determine a booting mode, based on use information of the electronic apparatus, determine a priority order and an affinity of each of the tasks for the determined booting mode, based on the task-processing information of the tasks for the determined booting mode, and process the tasks for the determined booting mode, based on the determined priority order and affinity of each of the tasks for the determined booting mode, to boot the electronic apparatus.

Abstract: In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.

Abstract: A system joins predicate evaluated column bitmaps having varying lengths. The system includes a column unifier for querying column values with a predicate generating an indicator bit for each of the column values that is then joined with the respective column value. The system also includes a bitmap generator for creating a column-major linear bitmap from the column values and indicator bits. The column unifier also determines an offset between adjacent indicator bits. The system also includes a converter for multiplying the column-major linear bitmap with a multiplier to shift the indicator bits into consecutive positions in the linear bitmap.

Abstract: A display apparatus and a method for displaying a highlight thereof are provided. The method for displaying a highlight on a display apparatus includes determining a shape and a size of a menu item selected by a user, determining a plurality of source images to be used to generate a highlight with respect to the menu item according to whether the highlight has symmetry based on the shape of the menu item, and generating the highlight with respect to the menu item by magnifying a size of the plurality of source images according to the size of the menu item and displaying the generated highlight.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.

Abstract: A superjunction semiconductor device includes a first semiconductor layer doped with a first conductivity type; an active region formed on the first semiconductor layer, the active region including a drift layer; and a termination region disposed to surround the active region, the termination region including a lower edge region disposed on a side surface of the drift layer and an upper edge region disposed on the lower edge region, wherein the upper edge region includes a lower charge balance region disposed on the lower edge region, the lower charge balance region having a second conductivity type different from the first conductivity type, and an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity type.