Patents by Inventor Jae Gon Lee

Jae Gon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12287751
    Abstract: A computing system includes a first storage device, a second storage device, a memory device, and a compute express link (CXL) switch. The memory device stores first map data of the first storage device and second map data of the second storage device. The CXL switch is connected with the first storage device, the second storage device, and an external host through a first interface, and arbitrates communications between the first storage device, the second storage device, and the external host. The first storage device is connected with the memory device through a second interface. The second storage device is connected with the memory device through a third interface. The first interface, the second interface, and the third interface are physically separated from each other.
    Type: Grant
    Filed: April 5, 2023
    Date of Patent: April 29, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghan Lee, Jae-gon Lee, Chon Yong Lee
  • Publication number: 20250068355
    Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Chon Yong LEE, Jae-Gon LEE, Kyung-Chang RYOO, Kyunghan LEE, Hyeyoung RYU
  • Publication number: 20250036292
    Abstract: A memory device is provided. The memory device includes: a buffer memory; a nonvolatile backup memory; and a memory controller configured to: store map data corresponding to an external storage device in the buffer memory; provide, in response to a request from the external storage device, an address pair corresponding to the request, from among address pairs of the map data, to the external storage device; and back up, in response to a sudden power-off event, the map data to the nonvolatile backup memory.
    Type: Application
    Filed: October 17, 2024
    Publication date: January 30, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghan LEE, Seongsik HWANG, Chon Yong LEE, Jae-Gon LEE
  • Publication number: 20250036521
    Abstract: An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.
    Type: Application
    Filed: July 11, 2024
    Publication date: January 30, 2025
    Inventors: Myungkyu Lee, Seongmuk Kang, Jae-Gon Lee, Kyomin Sohn, Yeonggeol Song, Kijun Lee
  • Patent number: 12198053
    Abstract: An integrated circuit included in a device for performing a neural network operation includes a buffer configured to store feature map data in units of cells each including at least one feature, wherein the feature map data is for use in the neural network operation; and a multiplexing circuit configured to receive the feature map data from the buffer, and output extracted data by extracting feature data of one of features that are included within a plurality of cells in the received feature map data, the features each corresponding to an identical coordinate value.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: January 14, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-seok Park, Jin-ook Song, Jae-gon Lee, Yun-kyo Cho
  • Patent number: 12175093
    Abstract: A memory device is provided. The memory device includes: a buffer memory; a nonvolatile backup memory; and a memory controller configured to: store map data corresponding to an external storage device in the buffer memory; provide, in response to a request from the external storage device, an address pair corresponding to the request, from among address pairs of the map data, to the external storage device; and back up, in response to a sudden power-off event, the map data to the nonvolatile backup memory.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: December 24, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghan Lee, Seongsik Hwang, Chon Yong Lee, Jae-Gon Lee
  • Patent number: 12164802
    Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: December 10, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chon Yong Lee, Jae-Gon Lee, Kyung-Chang Ryoo, Kyunghan Lee, Hyeyoung Ryu
  • Patent number: 12130657
    Abstract: A semiconductor device includes an intellectual property (IP) block, a clock management unit, a critical path monitor (CPM), and a CPM clock manager included in the clock management unit. The clock management unit is configured to receive a clock request signal, indicating whether the IP block requires a clock signal, from the IP block and perform clock gating for the IP block based on the received clock request signal. The CPM is configured to monitor the clock signal provided to the IP block to adjust at least one of a frequency of the clock signal provided to the IP block and a voltage supplied to the IP block. The CPM clock manager is configured to perform the clock gating for the CPM.
    Type: Grant
    Filed: September 21, 2023
    Date of Patent: October 29, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Gon Lee, Jae Young Lee, Se Hun Kim
  • Patent number: 11957164
    Abstract: A method for manufacturing a flavor capsule of tobacco according to an embodiment of the present disclosure may comprise: a membrane manufacturing step for manufacturing a membrane of a flavor capsule by a membrane manufacturing part that manufactures a membrane; a capsule manufacturing step for manufacturing the flavor capsule using an apparatus for manufacturing a capsule with the membrane manufactured during the membrane manufacturing step and a flavored liquid to be held in the membrane; and a hardening step for hardening the flavor capsule.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 16, 2024
    Assignee: KT&G CORPORATION
    Inventors: Ick Joong Kim, Ali Jeong Bang, Jung Seop Hwang, Sang Jin Nam, Jae Gon Lee, Han Joo Chung
  • Publication number: 20240012446
    Abstract: A semiconductor device includes an intellectual property (IP) block, a clock management unit, a critical path monitor (CPM), and a CPM clock manager included in the clock management unit. The clock management unit is configured to receive a clock request signal, indicating whether the IP block requires a clock signal, from the IP block and perform clock gating for the IP block based on the received clock request signal. The CPM is configured to monitor the clock signal provided to the IP block to adjust at least one of a frequency of the clock signal provided to the IP block and a voltage supplied to the IP block. The CPM clock manager is configured to perform the clock gating for the CPM.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Inventors: Jae Gon Lee, Jae Young Lee, Se Hun Kim
  • Patent number: 11860687
    Abstract: A semiconductor device includes an intellectual property (IP) block, a clock management unit, a critical path monitor (CPM), and a CPM clock manager included in the clock management unit. The clock management unit is configured to receive a clock request signal, indicating whether the IP block requires a clock signal, from the IP block and perform clock gating for the IP block based on the received clock request signal. The CPM is configured to monitor the clock signal provided to the IP block to adjust at least one of a frequency of the clock signal provided to the IP block and a voltage supplied to the IP block. The CPM clock manager is configured to perform the clock gating for the CPM.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Gon Lee, Jae Young Lee, Se Hun Kim
  • Publication number: 20230376238
    Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 23, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chon Yong LEE, Jae-Gon Lee, Kyung-Chang Ryoo, Kyunghan Lee, Hyeyoung Ryu
  • Publication number: 20230376216
    Abstract: A memory device is provided. The memory device includes: a buffer memory; a nonvolatile backup memory; and a memory controller configured to: store map data corresponding to an external storage device in the buffer memory; provide, in response to a request from the external storage device, an address pair corresponding to the request, from among address pairs of the map data, to the external storage device; and back up, in response to a sudden power-off event, the map data to the nonvolatile backup memory.
    Type: Application
    Filed: April 6, 2023
    Publication date: November 23, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghan LEE, Seongsik HWANG, Chon Yong LEE, Jae-Gon LEE
  • Publication number: 20230359566
    Abstract: A computing system includes a host, a memory, and a storage device. The memory includes a volatile memory and a memory controller. The storage device is connected with the host through a first interface and includes a nonvolatile memory and a storage controller, the storage device communicating with the host through a first port, communicating with the memory through a second port, and managing the memory. The memory is connected with the storage device through a second interface that is physically separated from the first interface. In an initialization operation, the storage controller sends map data that is stored in the nonvolatile memory to the memory through the second interface. In the initialization operation, the memory controller stores the map data in the volatile memory.
    Type: Application
    Filed: December 7, 2022
    Publication date: November 9, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: KYUNGHAN LEE, JAE-GON LEE, CHON YONG LEE
  • Publication number: 20230359567
    Abstract: A computing device includes a storage device and a memory. The storage device includes nonvolatile and internal buffer memories, and a storage controller that controls the nonvolatile and internal buffer memories and communicates with a bus. The memory includes a buffer memory and a memory controller that controls the buffer memory and communicates with the bus. The nonvolatile memory stores user data and map data. In an initialization operation, the storage controller sends the map data to the memory through the bus, and the memory controller stores the map data that is transferred from the storage device through the bus, in the buffer memory. After the initialization operation, the memory controller sends partial map data of the map data to the storage device through the bus, and the storage controller stores the partial map data that is transferred from the memory through the bus, in the internal buffer memory.
    Type: Application
    Filed: April 18, 2023
    Publication date: November 9, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: KYUNGHAN LEE, JAE-GON LEE, Chon Yong LEE
  • Publication number: 20230359389
    Abstract: A system includes a first compute express link (CXL) storage device, a second CXL storage device, a first CXL memory device, and a CXL switch connected to the first CXL storage device, the second CXL storage device and the first CXL memory device through a CXL interface, the CXL switch configured to arbitrate communications between the first CXL storage device and the second CXL storage device, and the first CXL memory device. The first CXL memory device is configured to store first map data of the first CXL storage device and second map data of the second CXL storage device, the first CXL storage device is configured to exchange at least a portion of the first map data with the first CXL memory device through the CXL switch, and the second CXL storage device is configured to exchange at least a portion of the second map data with the first CXL memory device through the CXL switch.
    Type: Application
    Filed: April 4, 2023
    Publication date: November 9, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: KYUNGHAN LEE, JAE-GON LEE, Chon Yong LEE
  • Publication number: 20230359578
    Abstract: A computing system includes a first storage device, a second storage device, a memory device, and a compute express link (CXL) switch. The memory device stores first map data of the first storage device and second map data of the second storage device. The CXL switch is connected with the first storage device, the second storage device, and an external host through a first interface, and arbitrates communications between the first storage device, the second storage device, and the external host. The first storage device is connected with the memory device through a second interface. The second storage device is connected with the memory device through a third interface. The first interface, the second interface, and the third interface are physically separated from each other.
    Type: Application
    Filed: April 5, 2023
    Publication date: November 9, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyunghan LEE, Jae-gon LEE, Chon Yong LEE
  • Publication number: 20230359394
    Abstract: An operating method of a memory device which communicates with a first storage device and a second storage device through an interface circuit is provided. The method includes receiving, from a host device, a first request including a command and a first logical block address; obtaining, based on the first logical block address, a first physical block address with reference to first map data dedicated for the first storage device; and sending, to the first storage device through the interface circuit, a second request including the first physical block address and the command.
    Type: Application
    Filed: April 13, 2023
    Publication date: November 9, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Gon Lee, Kyunghan Lee, Chon Yong Lee
  • Publication number: 20230359379
    Abstract: A method of operating a computing system which includes a plurality of storage devices, a memory device, and a switch, is provided. The method includes: providing a first mapping request including first metadata corresponding to first user data to the memory device through the switch, by a first storage device of the plurality of storage devices; identifying a first standard corresponding to the first metadata based on the first mapping request, by the memory device; and generating first map data indicating a relationship between a first physical block address and a first logical block address of the first user data based on the first standard, by the memory device.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 9, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: CHON YONG LEE, KYUNGHAN LEE, SEONGSIK HWANG, JAE-GON LEE, KYUNG-CHANG RYOO
  • Publication number: 20230350832
    Abstract: A storage device includes a nonvolatile memory device that stores user data, and a storage controller that controls the nonvolatile memory device under control of a host device. The storage controller includes a storage interface circuit that communicates with the host device through a compute express link (CXL) interface, a NAND interface circuit that communicates with the nonvolatile memory device, and a processor that loads map data from an external memory device through the storage interface circuit and controls the nonvolatile memory device through the NAND interface circuit based on the map data.
    Type: Application
    Filed: April 10, 2023
    Publication date: November 2, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghan LEE, Jae-Gon LEE, Chon Yong LEE