Abstract: There is provided an image encoding/decoding method and apparatus. The image decoding method comprises decoding size information of a quantization group from a bitstream, acquiring a delta quantization parameter of a current block on the basis of the size information of the quantization group, and deriving a quantization parameter for the current block on the basis of the delta quantization parameter.

Abstract: There is provided an video encoding/decoding method and apparatus. The video decoding method comprises acquiring a bitstream including a predetermined context element, performing at least one of a context model determination, a probability update, and a probability interval determination on the predetermined syntax element, and arithmetically decoding the predetermined syntax element on the basis of a result of the performance.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: A memory module includes a random access memory (RAM) device that includes a first storage region and a second storage region, a nonvolatile memory device, and a controller that controls the RAM device or the nonvolatile memory device under control of a host. The controller includes a data buffer that temporarily stores first data received from the host, and a buffer returning unit that transmits first release information to the host when the first data are moved from the data buffer to the first storage region or the second storage region of the RAM device and transmits second release information to the host when the first data are moved from the second storage region to the nonvolatile memory device.

Abstract: A method of page size aware scheduling and a non-transitory computer-readable storage medium having recorded thereon a computer program for executing the method of page size aware scheduling are provided. The method includes determining a size of a media page; determining if the media page is open or closed; performing, by a memory controller, a speculative read operation if the media page is determined to be open; and performing, by the memory controller, a regular read operation if the media page is determined to be closed.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

Abstract: An apparatus for manufacturing a flavor capsule of tobacco according to an embodiment of the present disclosure may comprise: a membrane tank for storing a membrane; a flavored liquid tank for storing a flavored liquid; and a nozzle to which the membrane is supplied from the membrane tank, to which the flavored liquid is supplied from the flavored liquid tank, and through which the flavored liquid is discharged while being enveloped in the membrane, so as to form the initial shape of a flavor capsule, wherein the membrane tank is equipped with a temperature adjustment unit for lowering the temperature of the membrane tank over time in order to preserve the viscosity of the membrane.

Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scaled gate contact and source/drain cap and methods of manufacture. The structure includes: a gate structure comprising an active region; source and drain contacts adjacent to the gate structure; a capping material over the source and drain contacts; a gate contact formed directly above the active region of the gate structure and over the capping material; a U-shape dielectric material around the gate contact, above the source and drain contacts; and a contact in direct electrical contact to the source and drain contacts.

Abstract: An apparatus for manufacturing a flavor capsule of tobacco according to an embodiment of the present disclosure may comprise: a membrane tank for storing a membrane; a flavored liquid tank for storing a flavored liquid; and a nozzle to which the membrane is supplied from the membrane tank, to which the flavored liquid is supplied from the flavored liquid tank, and through which the flavored liquid is discharged while being enveloped in the membrane, so as to form the initial shape of a flavor capsule, wherein the membrane tank is equipped with a temperature adjustment unit for lowering the temperature of the membrane tank over time in order to preserve the viscosity of the membrane.

Abstract: In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

Abstract: A method for manufacturing a flavor capsule of tobacco according to an embodiment of the present disclosure may comprise: a membrane manufacturing step for manufacturing a membrane of a flavor capsule by a membrane manufacturing part that manufactures a membrane; a capsule manufacturing step for manufacturing the flavor capsule using an apparatus for manufacturing a capsule with the membrane manufactured during the membrane manufacturing step and a flavored liquid to be held in the membrane; and a hardening step for hardening the flavor capsule.

Abstract: One illustrative integrated circuit product disclosed herein includes a short-channel transistor device and a long-channel transistor device formed above a semiconductor substrate, wherein a first gate structure for the short-channel transistor device includes a short-channel WFM layer with a first upper surface that is positioned at a first distance above an upper surface of the semiconductor substrate, and wherein a second gate structure for the long-channel transistor device includes a long-channel WFM layer with a second upper surface that is positioned at a second distance above the upper surface of the semiconductor substrate, wherein the first distance is greater than the second distance.

Abstract: One illustrative method disclosed herein includes forming 1st and 2nd sacrificial gate structures for, respectively, 1st and 2nd devices, removing 1st and 2nd sacrificial gate electrodes from the 1st and 2nd sacrificial gate structures so as to at least partially define, respectively, 1st and 2nd replacement gate (RMG) cavities, and removing the 2nd sacrificial gate insulation layer from the 2nd RMG cavity while leaving the 1st sacrificial gate insulation layer in position in the 1st RMG cavity. The method also includes forming a conformal gate insulation layer in both the 1st and 2nd RMG cavities, removing the conformal gate insulation layer and the 1st sacrificial gate insulation layer from the 1st RMG cavity while leaving the conformal gate insulation layer in the 2nd RMG cavity, and performing an oxidation process to form an interfacial gate insulation layer only in the 1st RMG cavity.

Abstract: Provided is a directional monopole array antenna using a hybrid ground plane in which a plurality of monopole antennas are connected in a form of an array, wherein the monopole antennas includes: a ground plane designed to be divided into a PMC (perfect magnetic conductor) and a PEC (perfect electric conductor) such that a surface current induced in the PEC flows in a direction; and an antenna device vertically disposed in the ground plane.