Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: The present disclosure provides a waveguide display apparatus. The waveguide waveguide display apparatus of the present disclosure is a waveguide display apparatus for correcting curved surface reflection distortion, the waveguide display apparatus including a waveguide for guiding light inputted from the outside; a first diffractive optical element disposed at the waveguide, and diffracting the light inputted from the outside to the inside of the waveguide; and a second diffractive optical element disposed at the waveguide, and diffracting the light guided by the waveguide to output a plurality of diffracted lights in a direction of a curved surface reflector located outside, wherein the second diffractive optical element has a structure of a diffraction grating corresponding to a curvature of the curved surface reflector such that the diffracted lights are reflected at different locations of the curved surface reflector in directions parallel to each other.

Abstract: A method for manufacturing a flavor capsule of tobacco according to an embodiment of the present disclosure may comprise: a membrane manufacturing step for manufacturing a membrane of a flavor capsule by a membrane manufacturing part that manufactures a membrane; a capsule manufacturing step for manufacturing the flavor capsule using an apparatus for manufacturing a capsule with the membrane manufactured during the membrane manufacturing step and a flavored liquid to be held in the membrane; and a hardening step for hardening the flavor capsule.

Abstract: Disclosed herein are a decoding method and apparatus and an encoding method and apparatus for deriving an intra-prediction mode. An intra-prediction mode may be derived using a method for deriving an intra-prediction mode based on a neighbor block of the target block, a method for deriving an intra-prediction mode using signaling of the intra-prediction mode of the target block, or a method for deriving an adaptive intra-prediction mode based on the type of a target slice. An MPM list may be used to derive the intra-prediction mode, and a temporal neighbor block or the like may be used to configure the MPM list.

Abstract: The present invention provides a multilayer circuit board and a method for manufacturing the same for improving a bowing problem that occurs when manufacturing the multilayer circuit board. A multilayer circuit board according to the present invention is a board having a patterned layer that functions as a circuit a base layer, and includes: a second pattern layer formed on one side of the base layer; a first pattern layer formed on the second pattern layer; and an interlayer insulating layer formed between the first pattern layer and the second pattern layer, the interlayer insulating layer being partially formed on the second pattern layer so as to correspond to a region where the first pattern layer is formed.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: Disclosed herein are a decoding method and apparatus and an encoding method and apparatus that perform inter-prediction using a motion vector predictor. For a candidate block in a col picture, a scaled motion vector is generated based on a motion vector of the candidate block. When the scaled motion vector indicates a target block, a motion vector predictor of the target block is generated based on the motion vector of the candidate block. The motion vector predictor is used to derive the motion vector of the target block in a specific inter-prediction mode such as a merge mode and an AMVP mode.

Abstract: Disclosed are a method for inducing a prediction motion vector and an apparatus using the same. An image decoding method can include: a step of determining the information related to a plurality of spatial candidate prediction motion vectors from peripheral predicted blocks of a predicted target block; and a step of determining the information related to temporal candidate prediction motion vectors on the basis of the information related to the plurality of spatial candidate prediction motion vectors. Accordingly, the present invention can reduce complexity and can enhance coding efficiency when inducing the optimum prediction motion vector.

Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: A semiconductor device includes an intellectual property (IP) block, a clock management unit, a critical path monitor (CPM), and a CPM clock manager included in the clock management unit. The clock management unit is configured to receive a clock request signal, indicating whether the IP block requires a clock signal, from the IP block and perform clock gating for the IP block based on the received clock request signal. The CPM is configured to monitor the clock signal provided to the IP block to adjust at least one of a frequency of the clock signal provided to the IP block and a voltage supplied to the IP block. The CPM clock manager is configured to perform the clock gating for the CPM.

Abstract: A semiconductor device includes an intellectual property (IP) block, a clock management unit, a critical path monitor (CPM), and a CPM clock manager included in the clock management unit. The clock management unit is configured to receive a clock request signal, indicating whether the IP block requires a clock signal, from the IP block and perform clock gating for the IP block based on the received clock request signal. The CPM is configured to monitor the clock signal provided to the IP block to adjust at least one of a frequency of the clock signal provided to the IP block and a voltage supplied to the IP block. The CPM clock manager is configured to perform the clock gating for the CPM.

Abstract: A memory device is provided. The memory device includes: a buffer memory; a nonvolatile backup memory; and a memory controller configured to: store map data corresponding to an external storage device in the buffer memory; provide, in response to a request from the external storage device, an address pair corresponding to the request, from among address pairs of the map data, to the external storage device; and back up, in response to a sudden power-off event, the map data to the nonvolatile backup memory.

Abstract: A method of operating storage devices, a memory device, a host device, and a switch, is provided. The method includes: receiving, by the memory device, a first request corresponding to target user data from the host device; generating, by the memory device, first input/output (I/O) stream information based on telemetry information corresponding to the storage devices and map data in a buffer memory of the memory device based on the first request, wherein the first I/O stream information indicates a data path between a first storage device of the storage devices and the host device; providing, by the memory device, a first redirection request including the first request and the first I/O stream information to the host device or the first storage device through the switch; and processing the target user data according to the first I/O stream information in the first redirection request.

Abstract: A computing system includes a host, a memory, and a storage device. The memory includes a volatile memory and a memory controller. The storage device is connected with the host through a first interface and includes a nonvolatile memory and a storage controller, the storage device communicating with the host through a first port, communicating with the memory through a second port, and managing the memory. The memory is connected with the storage device through a second interface that is physically separated from the first interface. In an initialization operation, the storage controller sends map data that is stored in the nonvolatile memory to the memory through the second interface. In the initialization operation, the memory controller stores the map data in the volatile memory.

Abstract: A method of operating a computing system which includes a plurality of storage devices, a memory device, and a switch, is provided. The method includes: providing a first mapping request including first metadata corresponding to first user data to the memory device through the switch, by a first storage device of the plurality of storage devices; identifying a first standard corresponding to the first metadata based on the first mapping request, by the memory device; and generating first map data indicating a relationship between a first physical block address and a first logical block address of the first user data based on the first standard, by the memory device.

Abstract: An operating method of a memory device which communicates with a first storage device and a second storage device through an interface circuit is provided. The method includes receiving, from a host device, a first request including a command and a first logical block address; obtaining, based on the first logical block address, a first physical block address with reference to first map data dedicated for the first storage device; and sending, to the first storage device through the interface circuit, a second request including the first physical block address and the command.

Abstract: A computing system includes a first storage device, a second storage device, a memory device, and a compute express link (CXL) switch. The memory device stores first map data of the first storage device and second map data of the second storage device. The CXL switch is connected with the first storage device, the second storage device, and an external host through a first interface, and arbitrates communications between the first storage device, the second storage device, and the external host. The first storage device is connected with the memory device through a second interface. The second storage device is connected with the memory device through a third interface. The first interface, the second interface, and the third interface are physically separated from each other.

Abstract: A system includes a first compute express link (CXL) storage device, a second CXL storage device, a first CXL memory device, and a CXL switch connected to the first CXL storage device, the second CXL storage device and the first CXL memory device through a CXL interface, the CXL switch configured to arbitrate communications between the first CXL storage device and the second CXL storage device, and the first CXL memory device. The first CXL memory device is configured to store first map data of the first CXL storage device and second map data of the second CXL storage device, the first CXL storage device is configured to exchange at least a portion of the first map data with the first CXL memory device through the CXL switch, and the second CXL storage device is configured to exchange at least a portion of the second map data with the first CXL memory device through the CXL switch.

Abstract: A computing device includes a storage device and a memory. The storage device includes nonvolatile and internal buffer memories, and a storage controller that controls the nonvolatile and internal buffer memories and communicates with a bus. The memory includes a buffer memory and a memory controller that controls the buffer memory and communicates with the bus. The nonvolatile memory stores user data and map data. In an initialization operation, the storage controller sends the map data to the memory through the bus, and the memory controller stores the map data that is transferred from the storage device through the bus, in the buffer memory. After the initialization operation, the memory controller sends partial map data of the map data to the storage device through the bus, and the storage controller stores the partial map data that is transferred from the memory through the bus, in the internal buffer memory.