Patents by Inventor Jae-Hee Oh

Jae-Hee Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250054477
    Abstract: Provided are a sound amplifying block formed of a permeable material and an air adsorbing material and having a layered structure and a method of manufacturing the same. The sound amplifying block formed of a permeable material and an air adsorbing material and having a layered structure includes a porous grain formed by a first porous material that is an air adsorbing material that serves to amplify sound, a second porous material that is a permeable material and has a pore size and porosity greater than those of the first porous material, and a binder and a structural gap formed in a process of freezing the porous grain and formed between porous grains.
    Type: Application
    Filed: December 16, 2022
    Publication date: February 13, 2025
    Inventors: Yong-Hee Oh, Jae-Hwa Lim
  • Publication number: 20250029197
    Abstract: A shared vehicle dispatch system dispatches shared vehicles based on driver grades classified by learning user driving patterns, and a shared vehicle dispatch method uses the shared vehicle dispatch system. The shared vehicle dispatch system includes a shared vehicle having a vehicle controller configured to learn driving pattern information of a user, a user terminal, operated by the user, equipped with a dedicated application installed for requesting the dispatch of the shared vehicle, and an operation server communicating with the shared vehicle to receive the learned driving pattern information, where the operation server may determine a driver grade for the user who operated the shared vehicle based on the received driving pattern information.
    Type: Application
    Filed: October 27, 2022
    Publication date: January 23, 2025
    Inventors: Ho Kyung Kim, Sil Lo Jin, In Jae Kwak, Sang Hwan Oh, Sang Hoon Kim, Dae Woo Kim, Nam Chul Paik, Hyeong Tae Noh, Se Hee Byun
  • Patent number: 12207046
    Abstract: The present disclosure provides a microspeaker enclosure including a block formed of a porous material. The microspeaker enclosure including a block formed of a porous material includes a microspeaker, an enclosure case in which the microspeaker is mounted, the enclosure case including a back volume communicating with the microspeaker, a porous block installed in the back volume, having 3-nm pores having air adsorption performance and 6-nm pores serving as a passage for air circulation in a predetermined ratio, and including porous particles combined as a block, and a film attached to one surface of the porous block.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: January 21, 2025
    Assignee: EM-TECH Co., Ltd.
    Inventors: Yong Hee Oh, Jae Hwa Lim
  • Publication number: 20230317596
    Abstract: A semiconductor device includes a substrate including a first surface and a second surface opposite to the first surface; an active pattern extending in a first direction on the first surface of the substrate; a first source/drain contact including a first portion connected to a source/drain region of the active pattern, and a second portion extending from the first portion in the first direction or in a second direction intersecting the first direction; a power rail providing a voltage on the second surface of the substrate; a through electrode connected to the power rail and penetrating the substrate; and a landing pad connecting the through electrode and the second portion of the source/drain contact.
    Type: Application
    Filed: February 8, 2023
    Publication date: October 5, 2023
    Inventors: Ji Hyung KIM, Jae Hee OH, Je Gwan HWANG, Jeong Hoon AHN
  • Publication number: 20230170289
    Abstract: An interposer structure includes an interposer substrate, an interlayer insulating layer on an upper surface of the interposer substrate, a capacitor structure inside the interlayer insulating layer, a first via which penetrates the interlayer insulating layer in a vertical direction, the first via being connected to the capacitor structure, an insulating layer on the interlayer insulating layer, a second via which penetrates the insulating layer in the vertical direction, the second via being connected to the first via, and a through via which completely penetrates each of the interposer substrate, the interlayer insulating layer, and the insulating layer in the vertical direction, an upper surface of the through via being coplanar with an upper surface of the second via.
    Type: Application
    Filed: July 8, 2022
    Publication date: June 1, 2023
    Inventors: Woo Seong JANG, Won Ji PARK, Jeong Hoon AHN, Jae Hee OH, Ji Hyung KIM, Shaofeng DING, Seok Jun HONG, Je Gwan HWANG
  • Patent number: 9117595
    Abstract: An electronic component with terminal strips joined to end faces of external electrodes via a solder is characterized in that two plate-like supports of each terminal strip are formed by bending two plate-like parts projecting outward in a line-symmetrical manner from both side edges of a plate-like leg in the width direction such that at least tips of the thickness surfaces on the electronic component sides of the two plate-like parts are positioned below an external electrode of the electronic component, and the electronic component is supported from below by the tips of the thickness surfaces on the electronic component sides of the four plate-like supports. Slipping of the electronic component from both terminal strips due to melting of the solder can be suppressed in a reliable manner.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 25, 2015
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Naoki Saito, Katsunosuke Haga, Jae Hee Oh
  • Patent number: 8958229
    Abstract: A nonvolatile memory device includes multiple variable resistive elements formed on a substrate; multiple bit lines formed on the variable resistive elements, extended in a first direction, and separated from each other by a first pitch; multiple circuit word lines formed on the multiple bit lines, extended in a second direction, and separated from each other by a second pitch; and multiple circuit word lines formed on the multiple bit lines, extended in the first direction, and separated from each other by a third pitch, wherein the third pitch of the multiple circuit word lines is larger than the first pitch of the multiple bit lines.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jae-Hee Oh, Sung-Won Kim
  • Patent number: 8791448
    Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-in Kim, Jae-hee Oh, Jun-hyok Kong, Sung-ho Eun, Yong-tae Oh
  • Patent number: 8724411
    Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Young Kim, Ki Whan Song, Jae Hee Oh, Ji-Hyun Jeong
  • Publication number: 20140063687
    Abstract: An electronic component with terminal strips joined to end faces of external electrodes via a solder is characterized in that two plate-like supports of each terminal strip are formed by bending two plate-like parts projecting outward in a line-symmetrical manner from both side edges of a plate-like leg in the width direction such that at least tips of the thickness surfaces on the electronic component sides of the two plate-like parts are positioned below an external electrode of the electronic component, and the electronic component is supported from below by the tips of the thickness surfaces on the electronic component sides of the four plate-like supports. Slipping of the electronic component from both terminal strips due to melting of the solder can be suppressed in a reliable manner.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 6, 2014
    Applicant: TAIYO YUDEN CO., LTD.
    Inventors: Naoki SAITO, Katsunosuke HAGA, Jae Hee OH
  • Patent number: 8518790
    Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-in Kim, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
  • Publication number: 20130187119
    Abstract: Semiconductor memory devices having strapping contacts are provided, the devices include cell regions and strapping regions between adjacent cell regions in a first direction. Active patterns, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines, extending in the first direction throughout the cell regions and strapping regions, are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines, extending in the second direction, intersect the active patterns and first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions.
    Type: Application
    Filed: September 28, 2012
    Publication date: July 25, 2013
    Inventors: Jung-in Kim, Jae-hee Oh, Jun-hyok Kong, Sung-ho Eun, Yong-tae Oh
  • Patent number: 8493769
    Abstract: An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ho Eun, Jae-Hee Oh
  • Publication number: 20130143382
    Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 6, 2013
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Jung-in KIM, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
  • Patent number: 8384060
    Abstract: Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: February 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Chang Ryoo, Jae-Hee Oh, Jung-Hoon Park, Hyeong-Jun Kim, Dong-Won Lim
  • Publication number: 20130009125
    Abstract: A semiconductor device includes an insulation layer including a cell contact hole, and a switching device in the cell contact hole, at least a part of a top surface of the switching device being inclined with respect to an axial direction of the cell contact hole.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 10, 2013
    Inventors: Jong-hyun PARK, Jae-hee Oh, Kyu-sul Park
  • Patent number: 8324067
    Abstract: A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-in Kim, Jae-Hee Oh, Hyunho Kim, Ji-Hyun Jeong
  • Publication number: 20120092946
    Abstract: A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 19, 2012
    Inventors: Jin-Young KIM, Ki Whan SONG, Jae Hee OH, Ji-Hyun JEONG
  • Patent number: 8148193
    Abstract: A semiconductor device such as a phase change memory device includes a semiconductor substrate including an active region, a conductive pattern disposed to expose the active region, an interlayer dielectric pattern provided on the conductive pattern and including an opening formed on the exposed active region and a contact hole spaced apart from the opening to expose the conductive pattern, a semiconductor pattern and a heater electrode pattern electrically connected to the exposed active region and provided in the opening, a contact plug connected to the exposed conductive pattern and provided to fill the contact hole, and a phase change material layer provided on the heater electrode pattern.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jae-Hee Oh
  • Patent number: 8143610
    Abstract: A semiconductor phase-change memory device comprises a data line disposed on a semiconductor substrate and a data storage structure disposed under the data line and having a concave portion extending in a direction along the data line. A data contact structure is configured to contact the data storage structure, and having a lower portion filling the concave portion of the data storage structure and an upper portion surrounding at least a lower portion of the data line. Each of sidewalls of the data storage structure is disposed at substantially the same plane as a corresponding one of sidewalls of the upper portion of the data contact structure.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Park, Jae-Hee Oh, Sung-Ho Eun