Abstract: Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.

Abstract: Capacitors for semiconductor devices and methods of fabricating such capacitors are provided. The disclosed capacitor comprises an interlayer dielectric layer (ILD) pattern having an opening exposing a portion of the underlying semiconductor substrate, a silicide pattern formed on the exposed substrate, and a lower electrode covering an inner wall and bottom of the opening. A dielectric layer is formed on the lower electrode, and an upper electrode is disposed on the dielectric layer. The dielectric layer preferably comprises a high k-dielectric layer such as tantalum oxide. The disclosed method comprises forming an ILD pattern with an opening that exposes a portion of a semiconductor substrate forming an optional silicide pattern on the exposed substrate, forming a lower electrode on the inner wall of the opening, and sequentially forming a dielectric layer and an upper electrode on the resulting structure.

Abstract: Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

Abstract: In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

Abstract: A method of forming a semiconductor device comprising: sequentially forming a supporting layer and a sacrificial layer over a semiconductor substrate; forming an opening by patterning the sacrificial layer and the supporting layer; forming a bottom electrode covering the inner wall and the bottom of the opening; removing the sacrificial layer by a wet etch process; and forming a dielectric layer and an upper electrode on the bottom electrode and the supporting layer, wherein the sacrificial layer is formed of a material having a faster wet etch rate than the supporting layer.

Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

Abstract: Provided are semiconductor devices having a system-on-chip (SOC) configuration that combines both a capacitor-based cell-array memory region and one or more MOS core/peripheral circuit/logic regions on a single chip and a method for manufacturing such devices. The manufacturing process reduces the number of additional photolithographic processes required and modifies the relationship between the sizing of various layers and/or structures to reduce the fabrication cost and improve the reliability of the resulting devices. In particular, the capacitors for the memory region are formed in the same insulating layer as the first metal pattern for the core/peripheral circuit/logic regions of the devices, thereby producing capacitors and metal patterns of substantially the same height and thickness respectively. A landing structure may also be formed in the cell array region in combination with the first metal pattern for improving the contact process in the cell array region.

Abstract: A semiconductor memory device is provided. A first insulating layer having a gate electrode is formed on a semiconductor substrate. A second insulating layer is formed on the first insulating layer, and the second insulating layer has bit lines covered with bit line isolation layers, buried contact plugs formed between the bit lines, and a first metal contact plug connected to the semiconductor substrate through the first insulating layer. A silicon nitride layer is formed on the second insulating layer. A third insulating layer is formed on the silicon nitride layer, and the third insulating layer has a second metal contact plug connected to the first metal contact plug through the silicon nitride layer. The second insulating layer includes a first landing stud connected to the gate electrode through the first insulting layer. The bit lines include a direct contact plug under one of the bit line. The first landing stud is simultaneously formed with the direct contact plug.

Abstract: A method of forming a semiconductor device comprising: sequentially forming a supporting layer and a sacrificial layer over a semiconductor substrate; forming an opening by patterning the sacrificial layer and the supporting layer; forming a bottom electrode covering the inner wall and the bottom of the opening; removing the sacrificial layer by a wet etch process; and forming a dielectric layer and an upper electrode on the bottom electrode and the supporting layer, wherein the sacrificial layer is formed of a material having a faster wet etch rate than the supporting layer.

Abstract: A semiconductor memory device is provided. A first insulating layer having a gate electrode is formed on a semiconductor substrate. A second insulating layer is formed on the first insulating layer, and the second insulating layer has bit lines covered with bit line isolation layers, buried contact plugs formed between the bit lines, and a first metal contact plug connected to the semiconductor substrate through the first insulating layer. A silicon nitride layer is formed on the second insulating layer. A third insulating layer is formed on the silicon nitride layer, and the third insulating layer has a second metal contact plug connected to the first metal contact plug through the silicon nitride layer. The second insulating layer includes a first landing stud connected to the gate electrode through the first insulting layer. The bit lines include a direct contact plug under one of the bit line. The first landing stud is simultaneously formed with the direct contact plug.

Abstract: Method of fabricating a semiconductor memory device includes the steps of: forming a gate electrode on a silicon substrate; forming a first inter-layer dielectric layer (ILD1) on the silicon substrate; forming a cell pad poly between the gate electrodes in the cell area; forming a direct-contact plug (DC) on the cell pad poly in the cell area, and a first landing stud on the gate in the peripheral area; forming a bit line on the DC in the cell area and a second landing stud on the first landing stud; forming a second inter-layer dielectric layer (ILD2) on the ILD1; forming a silicon nitride layer on the ILD2; patterning the silicon nitride layer; simultaneously etching out a portion of the ILD2 in the cell area and a portion of the ILD2 and a portion of the ILD1 in the peripheral area; and simultaneously forming a plurality of buried contact plugs in the cell area and a first metal contact plug in the peripheral area.

Abstract: Capacitors for semiconductor devices and methods of fabricating such capacitors are provided. The disclosed capacitor comprises an interlayer dielectric layer (ILD) pattern having an opening exposing a portion of the underlying semiconductor substrate, a silicide pattern formed on the exposed substrate, and a lower electrode covering an inner wall and bottom of the opening. A dielectric layer is formed on the lower electrode, and an upper electrode is disposed on the dielectric layer. The dielectric layer preferably comprises a high k-dielectric layer such as tantalum oxide. The disclosed method comprises forming an ILD pattern with an opening that exposes a portion of a semiconductor substrate forming an optional silicide pattern on the exposed substrate, forming a lower electrode on the inner wall of the opening, and sequentially forming a dielectric layer and an upper electrode on the resulting structure.

Abstract: A contact structure in a semiconductor device and a method of forming the same are provided. The contact structure includes a lower interconnection having a capacitor upper electrode of memory cells; an interlayer dielectric layer formed on the lower interconnection and having a contact hole that exposes a portion of the lower interconnection; and an upper interconnection formed on the interlayer dielectric layer and electrically connected to the lower interconnection through the contact hole. The lower portion of the lower interconnection has a larger width than the bottom of the contact hole and extends downward or below the bottom of the contact hole so that the lower interconnection has a T-shape in cross-section. With these structures, the lower interconnection can be prevented from being pierced when the contact holes are formed. Consequently, stable and uniform contact resistance can be obtained.

Abstract: A contact structure in a semiconductor device including a dynamic random access memory (DRAM) and a method of forming the same are provided. The contact structure, which is formed in a peripheral circuit area or a logic circuit area of a semiconductor device including a DRAM having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area, includes a lower interconnection formed of the same material as a capacitor upper electrode of each of the plurality of DRAM cells; an interlayer dielectric layer formed on the lower interconnection and having a contact hole exposing a predetermined portion of the lower interconnection; and an upper interconnection formed on the interlayer dielectric layer and electrically connected to the lower interconnection through the contact hole. The lower portion of the lower interconnection has a larger area than the bottom of the contact hole and extends downward so that the lower interconnection has a T-shape in a cross-section view.

Abstract: A semiconductor memory device is provided. A first insulating layer having a gate electrode is formed on a semiconductor substrate. A second insulating layer is formed on the first insulating layer, and the second insulating layer has bit lines covered with bit line isolation layers, buried contact plugs formed between the bit lines, and a first metal contact plug connected to the semiconductor substrate through the first insulating layer. A silicon nitride layer is formed on the second insulating layer. A third insulating layer is formed on the silicon nitride layer, and the third insulating layer has a second metal contact plug connected to the first metal contact plug through the silicon nitride layer. The second insulating layer includes a first landing stud connected to the gate electrode through the first insulting layer. The bit lines include a direct contact plug under one of the bit line. The first landing stud is simultaneously formed with the direct contact plug.