Patents by Inventor Jae-Ho Min
Jae-Ho Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092298Abstract: An airbag device and a method for controlling deployment of the same are proposed. The airbag device is configured to protect a passenger by controlling an airbag cushion deployed toward the rear space of a seatback in an event of a vehicle collision, and the airbag device includes an airbag cushion deploying toward the rear space of the seatback, a sensor part detecting a seating status and a seating posture of a passenger with respect to each seat, and a controller, in an event of a collision, configured to change and control a deploying status of the airbag cushion and an inflation amount of the airbag cushion in response to the seating status and the seating posture of the passenger.Type: ApplicationFiled: December 14, 2022Publication date: March 21, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Jiwoon SONG, Dong Gil LEE, Sang Won HWANGBO, Byung Ho MIN, Jae Jun HARM
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Publication number: 20240092305Abstract: Disclosed are a shoulder airbag and an airbag cushion thereof that are capable of restricting an occupant from being moved upward along a seatback and from being abruptly pushed in a direction away from a collision side of a vehicle when vehicle collision occurs, thereby safely protecting the occupant. The shoulder airbag includes an airbag cushion mounted in a seatback and configured to be deployed so as to cover each of the shoulders of an occupant sitting in a seat in three axis directions.Type: ApplicationFiled: September 12, 2023Publication date: March 21, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Jiwoon SONG, Dong Gil LEE, Sang Won HWANGBO, Byung Ho MIN, Jae Jun HARM
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Patent number: 11934950Abstract: An apparatus for embedding a sentence feature vector according to an embodiment includes a sentence acquisitor configured to acquire a first sentence and a second sentence, each including one or more words; a vector extractor configured to extract a first feature vector corresponding to the first sentence and a second feature vector corresponding to the second sentence by independently inputting each of the first sentence and the second sentence into a feature extraction network; and a vector compressor configured to compress the first feature vector and the second feature vector into a first compressed vector and a second compressed vector, respectively, by independently inputting each of the first feature vector and the second feature vector into a convolutional neural network (CNN)-based vector compression network.Type: GrantFiled: October 26, 2020Date of Patent: March 19, 2024Assignee: SAMSUNG SDS CO., LTD.Inventors: Seong Ho Joe, Young June Gwon, Seung Jai Min, Ju Dong Kim, Bong Kyu Hwang, Jae Woong Yun, Hyun Jae Lee, Hyun Jin Choi
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Publication number: 20240002615Abstract: Disclosed are a polyimide film for a graphite sheet, the polyimide film having a thickness of 100 ?m or larger and a 1%-weight-loss thermal decomposition temperature of 480° C. or lower and/or an L* value of 40 or higher being measured with a colorimeter, a method of forming the same polyimide film, and a graphite sheet manufactured using the same polyimide film.Type: ApplicationFiled: November 26, 2021Publication date: January 4, 2024Inventors: Jae-Ho MIN, Dong-Young WON
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Patent number: 10971516Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.Type: GrantFiled: March 6, 2019Date of Patent: April 6, 2021Inventors: Sung-Soo Ahn, Yong-Hoon Son, Minhyuk Kim, Jae Ho Min, Daehyun Jang
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Publication number: 20200075627Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.Type: ApplicationFiled: March 6, 2019Publication date: March 5, 2020Inventors: SUNG-SOO AHN, YONG-HOON SON, MINHYUK KIM, JAE HO MIN, DAEHYUN JANG
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Patent number: 9978756Abstract: Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.Type: GrantFiled: January 23, 2017Date of Patent: May 22, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hyuk Kim, Seung-pil Chung, Jae-ho Min
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Patent number: 9865540Abstract: A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.Type: GrantFiled: July 12, 2016Date of Patent: January 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hyuk Kim, Jae-Ho Min, Jong-Kyoung Park, Seung-Pil Chung
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Publication number: 20170330887Abstract: Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.Type: ApplicationFiled: January 23, 2017Publication date: November 16, 2017Inventors: Hyuk Kim, Seung-pil Chung, Jae-ho Min
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Publication number: 20170117222Abstract: A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart from each other along a first direction with respect to a surface of substrate. Each of the gate lines includes step portion protruding in a second direction. The at least one etch-stop layer covers the step portion of at least one of the gate lines and includes conductive material. The channels extend through the gate lines in the first direction. The contacts extend through the at least one etch-stop layer and are on the step portions of the gate lines.Type: ApplicationFiled: July 12, 2016Publication date: April 27, 2017Inventors: Hyuk KIM, Jae-Ho MIN, Jong-Kyoung PARK, Seung-Pil CHUNG
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Patent number: 9385134Abstract: In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width.Type: GrantFiled: July 25, 2014Date of Patent: July 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Ho Min, Ki-Jeong Kim, Kyoung-Sub Shin, Dong-Hyun Kim
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Patent number: 9372401Abstract: A method of forming micropatterns separated over a misalignment margin includes forming a first mold pattern including a main pattern and a separation-assist pattern, forming a first spacer mask having a first width around the first mold pattern, forming a second mold pattern using the first spacer mask as an etch mask, forming a second spacer mask having a second width around the second mold pattern, and forming a target pattern using the second spacer mask as an etch mask.Type: GrantFiled: August 17, 2012Date of Patent: June 21, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-jeong Kim, Jae-ho Min, Kyoung-sub Shin, Dong-hyun Kim
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Patent number: 9070448Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.Type: GrantFiled: July 18, 2014Date of Patent: June 30, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Ho Min, O-lk Kwon, Bum-Soo Kim, Dong-Chan Kim, Myeong-Cheol Kim
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Publication number: 20140328125Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.Type: ApplicationFiled: July 18, 2014Publication date: November 6, 2014Inventors: Jae-Ho Min, O-lk Kwon, Bum-Soo Kim, Dong-Chan Kim, Myeong-Cheol Kim
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Patent number: 8846541Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.Type: GrantFiled: December 18, 2013Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Ho Min, O-Ik Kwon, Bum-Soo Kim, Dong-Chan Kim, Myeong-Cheol Kim
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Publication number: 20140106567Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Inventors: Jae-Ho Min, O-Ik Kwon, Bum-Soo Kim, Dong-Chan Kim, Myeong-Cheol Kim
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Patent number: 8637407Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.Type: GrantFiled: September 23, 2011Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Ho Min, O-Ik Kwon, Bum-Soo Kim, Dong-chan Kim, Myeong-cheol Kim
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Patent number: 8629052Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.Type: GrantFiled: October 16, 2012Date of Patent: January 14, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ju Park, Jae-ho Min, Myeong-cheol Kim, Dong-chan Kim, Jae-hwang Sim
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Patent number: 8617998Abstract: Methods of forming integrated circuit devices utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. A target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is removed to define an opening between the sidewall spacers. The first mask layer is selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. The target material layer is selectively etched using the third pattern as an etching mask.Type: GrantFiled: June 28, 2011Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-ho Min, Seong-soo Lee, Ki-jeong Kim
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Publication number: 20130048603Abstract: A method of forming micropatterns separated over a misalignment margin includes forming a first mold pattern including a main pattern and a separation-assist pattern, forming a first spacer mask having a first width around the first mold pattern, forming a second mold pattern using the first spacer mask as an etch mask, forming a second spacer mask having a second width around the second mold pattern, and forming a target pattern using the second spacer mask as an etch mask.Type: ApplicationFiled: August 17, 2012Publication date: February 28, 2013Inventors: Ki-jeong Kim, Jae-ho Min, Kyoung-sub Shin, Dong-hyun Kim