Abstract: Disclosed is a semiconductor device having a capacitor of large capacitance. The capacitor includes a first electrode portion which has a conductive structure formed on a semiconductor substrate, an insulating layer with pinholes in the conductive structure, and a conductive silicon layer grown through the pinholes, a second electrode portion on the first electrode portion, and a dielectric film formed between the first and second electrode portions. A method for manufacturing the device includes the steps of forming the first electrode portion by forming the conductive structure, forming the insulating layer, growing a silicon through the pinholes to form a conductive silicon layer, and forming the dielectric film and the second electrode portion. The capacitor can be formed with various shapes and is increased to 1.5 times or greater in capacitance while maintaining reliability comparable to that of a conventional one.

Abstract: Disclosed is a semiconductor device having a capacitor of large capacitance. The capacitor includes a first electrode portion which has a conductive structure formed on a semiconductor substrate, an insulating layer with pinholes in the conductive structure, and a conductive silicon layer grown through the pinholes, a second electrode portion on the first electrode portion, and a dielectric film formed between the first and second electrode portions. A method for manufacturing the device includes the steps of forming the first electrode portion by forming the conductive structure, forming the insulating layer, growing a silicon through the pinholes to form a conductive silicon layer, and forming the dielectric film and the second electrode portion. The capacitor can be formed with various shapes and is increased to 1.5 times or greater in capacitance while maintaining reliability comparable to that of a conventional one.

Abstract: Disclosed is a method comprising forming a first electrode by forming a conductive layer on a semiconductor substrate, forming an etching mask on the conductive layer, etching the conductive layer and defining the conductive layer into cell units; and forming a dielectric film and a second electrode or the first electrode. Also disclosed is a method comprising forming a first electrode by forming a conductive structure on a semiconductor substrate, forming an etching mask on the conductive structure and etching the conductive structure; and forming a dielectric film and a second electrode on the first electrode. An insulating layer including pin holes such as a silicon nitride layer is formed on the conductive structure or the conductive layer; which is exposed under an oxidative atmosphere. The surface portion of the conductive structure or conductive layer is oxidized to form silicon oxide islands to be used as an etching mask.

Abstract: A semiconductor device and a manufacturing method therefor are disclosed, the semiconductor device including a field oxide layer selectively formed on a semiconductor substrate for defining an active region; an electrically insulated gate electrode; a source and a drain region; a trench formed in the semiconductor substrate; an impurity-doped region formed at the surface of the trench; a first insulating layer a second conductive layer; a dielectric film; a third conductive layer; a fourth conductive layer; an etch blocking layer; a fifth conductive layer The manufacturing method comprises a plurality of processes for forming the above mentioned parts by applying various processes. According to the present invention, as both the impurity-doped polycrystalline silicon layer of the upper portion of the transistor and the inside of the trench including the impurity-doped region are simultaneously used as the first electrode of the capacitor, the surface area of the capacitor electrode can be made larger.

Abstract: A highly integrated semiconductor memory device comprises a plurality of memory cells formed by alternately disposing a stack-type capacitor cell and a combined stack-trench type capacitor cell both in row and column directions. Each storage electrode of the capacitor of the memory cell is extended to overlap with the storage electrode of the capacitor of the adjacent memory cell. The combined stack-trench type capacitor is formed into the substrate to increase the storage capacitance thereof which allow the storage capacitance of the stack-type capacitor to increase by extending the storage electrode of the capacitor. Due to the alternate arrangement of stack-trench type capacitor and stack-type capacitor, step coverage, leakage current and soft errors of stack-trench type capacitor are prevented.

Abstract: A highly integrated semiconductor memory device comprises a plurality of memory cells formed by alternately disposing a stack-type capacitor cell and a combined stack-trench type capacitor cell both in row and column directions. Each storage electrode of the capacitor of the memory cell is extended to overlap with the storage electrode of the capacitor of the adjacent memory cell. The combined stack-trench type capacitor is formed into the substrate to increase the storage capacitance thereof which allow the storage capacitance of the stack-type capacitor to increase by extending the storage electrode of the capacitor. Due to the alternate arrangement of stack-trench type capacitor and stack-type capacitor, step coverage, leakage current and soft errors of stack-trench type capacitor are prevented.

Abstract: A semiconductor device and a manufacturing method therefor are disclosed, the semiconductor device including a field oxide layer selectively formed on a semiconductor substrate for defining an active region; an electrically insulated gate electrode; a source and a drain region; a trench formed in the semiconductor substrate; an impurity-doped region formed at the surface of the trench; a first insulating layer; a second conductive layer; a dielectric film; a third conductive layer; a fourth conductive layer; an etch blocking layer; a fifth conductive layer. The manufacturing method comprises a plurality of processes for forming the above mentioned parts by applying various processes. According to the present invention, as both the impurity-doped polycrystalline silicon layer of the upper portion of the transistor and the inside of the trench including the impurity-doped region are simultaneously used as the first electrode of the capacitor, the surface area of the capacitor electrode can be made larger.