Abstract: A method for producing an aqueous solution containing nickel or cobalt includes: (A) a leaching step, which includes a first atmospheric pressure heating leaching step and a second atmospheric pressure heating leaching step, in which a raw material is heated and leached under an atmospheric pressure to form a leachate solution containing nickel, cobalt, and impurities; (B) a first extraction step of separating the leachate solution into a first filtrate containing nickel and impurities and a first organic layer containing cobalt and impurities by adding a first solvent extractant to the leachate solution; (C-i) a precipitation removal step of precipitating and removing impurities including magnesium, calcium, or a mixture thereof by adding a precipitating agent to the first filtrate; and (D-i) a target material precipitation step of selectively precipitating a nickel cake containing nickel by adding a neutralizing agent to the first filtrate.

Abstract: A semiconductor wafer test system for controlling the supply of power to a semiconductor wafer test apparatus is provided. The semiconductor wafer test system includes a test operating server and the semiconductor wafer test apparatus. The test operating server manages a wafer test schedule and allocates lots to a prober, which loads wafers into the semiconductor wafer test apparatus, in accordance with the wafer test schedule. The test operating server sends a mode switch request to the semiconductor wafer test apparatus in accordance with the wafer test schedule, and the semiconductor wafer test apparatus is switched to a waiting mode in response to receipt of a request to switch to the waiting mode from the test operating server, and is switched to a ready mode in response to receipt of a request to switch to the ready mode from the test operating server.

Abstract: A semiconductor test apparatus is provided. The semiconductor test apparatus includes: a test management unit determining a test mode, generating a test signal in accordance with the determined test mode, and transmitting the test signal to fail memories; and one or more fail memory boards including the fail memory, which store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals, wherein if the determined test mode is a first test mode, at least some of the failure memory boards are powered off.

Abstract: An apparatus for clamping a probe card may include a body portion, an inner clamping portion and a plurality of outer clamping portions. The body portion may be arranged between a printed circuit board (PCB) of the probe card and a test head. The inner clamping portion may be integrally formed with an upper surface of the body portion. The inner clamping portion may be configured to affix a central portion of the PCB to the test head. The outer clamping portions may be integrally formed with side surfaces of the body portion. The outer clamping portions may be configured to affix a portion surrounding the central portion of the PCB to the test head. Thus, a contact area between the clamping apparatus and the PCB may be increased.

Abstract: An apparatus for clamping a probe card may include a body portion, an inner clamping portion and a plurality of outer clamping portions. The body portion may be arranged between a printed circuit board (PCB) of the probe card and a test head. The inner clamping portion may be integrally formed with an upper surface of the body portion. The inner clamping portion may be configured to affix a central portion of the PCB to the test head. The outer clamping portions may be integrally formed with side surfaces of the body portion. The outer clamping portions may be configured to affix a portion surrounding the central portion of the PCB to the test head. Thus, a contact area between the clamping apparatus and the PCB may be increased.

Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse.

Abstract: A mobile System on Chip (SoC) comprises a microprocessor and a first memory controller configured to control a refresh of a first memory. A temperature sensor detects a temperature in the first memory. When first temperature information received from the temperature sensor indicates that the detected temperature deviates from a predetermined temperature range, the first memory controller controls the first memory so as not to perform a self refresh. When second temperature information received from the temperature sensor indicates that the detected temperature is in the predetermined temperature range, the first memory controller outputs a self refresh command to the first memory.

Abstract: A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.

Abstract: In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.

Abstract: Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.

Abstract: Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.

Abstract: In a layout structure of pads and a structure of pad used for a test or wire bonding of a semiconductor device, a size of at least one or more non-wire bonding pads is relatively small as compared with a size of at least one or more pads to be used for wire bonding of the semiconductor device. In the pad structure, a pad includes a wire bonding region that has an embossed surface for a portion of top metal layer within a determined pad size to improve the bonding process, and a probe tip contact region that does not have the embossed surface for a surface portion of the top metal layer within the determined pad size, so as to reduce wear of probe tip during testing of the device. Pad pitch can thereby be increased within a limited region, and peripheral circuits can be further formed in regions that would have been occupied in a conventional pad formation region. Higher integration of semiconductor devices and reduced wear of probe tip in probing is thereby realized.

Abstract: A semiconductor device that performs stable circuit operations is provided. The device includes: a pull-up driver for pulling up a first node in response to first states of input and control signals; a pull-down driver for pulling down a second node in response to a second state of the input signal; at least one fuse connected between the first node and the second node; a latch for generating an output signal to maintain the state of the second node; and a controller for generating the control signal that is maintained in a first state when the input signal is in the second state, and maintained in the first state and then transitioned to the second state after a predetermined delay time when the input signal is transitioned to the first state. In this construction, even if the fuse is incompletely cut during a process of cutting the fuse, the pull-up driver or the pull-down driver is turned off, thus preventing unnecessary current flow in advance.

Abstract: A bit line pre-charge circuit of a semiconductor memory device includes a pre-charge circuit connected between a pair of bit lines for pre-charging the pair of bit lines in response to a pre-charge control signal and a pre-charge voltage transmitting circuit for transmitting a pre-charge voltage to the pre-charge circuit in response to the pre-charge control signal. A voltage drop in a pre-charge voltage generation line may be prevented when a short circuit is formed between a word line and a pair of bit lines, and current consumption during a standby operation of the semiconductor memory device may also be reduced, by preventing current from flowing from the pair of bit lines to the pre-charge voltage generation line.

Abstract: A bit line pre-charge circuit of a semiconductor memory device includes a pre-charge circuit connected between a pair of bit lines for pre-charging the pair of bit lines in response to a pre-charge control signal and a pre-charge voltage transmitting circuit for transmitting a pre-charge voltage to the pre-charge circuit in response to the pre-charge control signal. A voltage drop in a pre-charge voltage generation line may be prevented when a short circuit is formed between a word line and a pair of bit lines, and current consumption during a standby operation of the semiconductor memory device may also be reduced, by preventing current from flowing from the pair of bit lines to the pre-charge voltage generation line.

Abstract: State change transition times of a semiconductor memory device is reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharging circuits and non-shared I/O lines which have only a single precharging circuit, effective contact resistance of the non-shared I/O lines are reduced by eliminating unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.

Abstract: A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

Abstract: A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and is connected to an active area surrounded by the power gate through the power contact.