Abstract: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

Abstract: A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

Abstract: A semiconductor device includes a device isolation layer disposed in a substrate and defining an active region, a first gate pattern on the active region, a first insulating layer on the substrate and the first gate pattern, a first body region on the first insulating layer, and a first substrate plug extending from the substrate into the first insulating layer, the first substrate plug penetrating the device isolation layer and contacting the substrate under the device isolation layer.

Abstract: A NAND flash memory device includes a plurality of stacked semiconductor layers, device isolation layer patterns disposed in predetermined regions of each of the plurality of semiconductor layers, the device isolation layers defining active regions, source and drain impurity regions in the active regions, a source line plug structure electrically connecting the source impurity regions, and a bit-line plug structure electrically connecting the drain impurity regions, wherein the source impurity regions are electrically connected to the semiconductor layers.

Abstract: A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

Abstract: Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.

Abstract: An inrush current prevention circuit for a DC-DC converter is provided and in preferred aspects comprises a switching element that transforms an input voltage by being switched on and off and outputs the transformed voltage. A filter filtrates the outputted voltage, transformed via the switching element, and outputs the filtrated voltage as an output voltage. A reference voltage generator generates a reference voltage. An error amplifier compares the reference voltage and output voltage and outputs an error signal. A Pulse Width Modulation (PWM) signal generator generates a PWM signal to switch on and off the switching element according to the error signal. An on-off circuit either transmits or isolates the PWM signal to the switching element. An Electronic Control Unit (ECU) controls the on-off circuit. Preferred systems of the invention can prevent an inrush current immediately following power input or during reactivation of the DC-DC converter.

Abstract: A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.

Abstract: According to an embodiment of the invention, a lower transistor is formed on a semiconductor substrate, and an upper thin film transistor is formed on the lower transistor. A body contact plug is formed to penetrate an upper gate electrode of the upper thin film transistor and a body pattern, and to electrically connect with a lower gate electrode of the lower transistor. The body contact plug uses a contact hole to apply an electrical signal to the upper gate electrode of the upper thin film transistor, so additional volume is not necessary. Since the upper gate electrode is electrically connected to the body pattern through the body contact plug, the floating body effect of the upper thin film transistor can be improved. Therefore, a semiconductor device is provided with the high performance required to realize a highly-integrated semiconductor device.

Abstract: An inrush current prevention circuit for a DC-DC converter is provided and in preferred aspects comprises a switching element that transforms an input voltage by being switched on and off and outputs the transformed voltage. A filter filtrates the outputted voltage, transformed via the switching element, and outputs the filtrated voltage as an output voltage. A reference voltage generator generates a reference voltage. An error amplifier compares the reference voltage and output voltage and outputs an error signal. A Pulse Width Modulation (PWM) signal generator generates a PWM signal to switch on and off the switching element according to the error signal. An on-off circuit either transmits or isolates the PWM signal to the switching element. An Electronic Control Unit (ECU) controls the on-off circuit. Preferred systems of the invention can prevent an inrush current immediately following power input or during reactivation of the DC-DC converter.

Abstract: An apparatus for restoring the cell data storage regions of the common memory in an asynchronous transfer mode (ATM) switch system, comprises a first multiplexer for multiplexing the cell data with the header and content data separated, a second multiplexer for multiplexing the addresses generated from a plurality of FIFO registers, an address checker for checking the addresses from the second multiplexer to generate a first and second address signals if the addresses are checked normal, an address memory storing all addresses of the common memory in error state to selectively convert the addresses into normal state according to the second address signal from the address checker, a controller for checking the address memory at predetermined intervals to restore an address stored in error state to a normal state, and an address multiplexer for generating an idle address to an IAP according to the first address signal and address restored signal.

Abstract: The present invention is related to a device and method for processing a cell group in a common memory switch, in which output ports in the common memory switch are divided into an individualized output port group associated with only one output port and a grouped output port group associated with a plurality of output ports, wherein each output port is assigned to a unique group number.