Abstract: Disclosed herein is a retraction device for laparoscopy in which a trocar needle including latching grooves formed at the side of the lower end thereof is inserted into a trocar tube, both ends of which are opened, to form a laparoscopic platform, the laparoscopic platform pierces an abdominal wall and the trocar needle is pushed into an abdominal cavity so that the latching grooves are exposed to the outside of the trocar tube, sutures connected to tissue retractors retracting tissues are hung on the latching grooves, and then the trocar needle of the laparoscopic platform is drawn upwards so that the latching grooves are inserted back into the trocar tube to fix the tissue retractors to the laparoscopic platform. The retraction device for laparoscopy prevents the tissues from being unnecessarily damaged due to retraction and facilitates convenient retraction of the tissues without the help of assistant's two hands.

Abstract: A bowel management system includes a waste collection catheter having at least two distinct sections. The first section is patient proximal when disposed in the patient's rectum and has durometer hardness in the range of about 50 A to about 90 A. The second catheter section is connected to the first section and has durometer hardness in the range of about 5 A to about 49 A. A selectively collapsible, substantially spherical retention balloon is attached coaxially and exterior of the first catheter section such that the proximal-most end of the retention balloon is coincident to the proximal-most end of the first section of the waste collection catheter, the substantially spherical retention balloon having an inflated size so as to be sufficiently large enough to retain the patient proximal end of the catheter in the patient's rectum without being so large as to trigger a defecatory response in the patient.

Abstract: A monitor apparatus for a laparoscopic surgery rotates images captured by a laparoscope as an endoscope and displayed on monitors for the laparoscopic surgery clockwise or counterclockwise according to commands for rotating the images by surgeons who use image rotation manipulation parts such that the images of surgical devices displayed on the monitors are arranged in the direction where the surgeons can actually manipulate the laparoscopic surgical devices most conveniently.

Abstract: A monitor apparatus for a laparoscopic surgery rotates images captured by a laparoscope as an endoscope and displayed on monitors for the laparoscopic surgery clockwise or counter-clockwise according to commands for rotating the images by surgeons who use image rotation manipulation parts such that the images of surgical devices displayed on the monitors are arranged in the direction where the surgeons can actually manipulate the laparoscopic surgical devices most conveniently.

Abstract: A bowel management system includes a waste collection catheter having at least two distinct sections. The first section is patient proximal when disposed in the patient's rectum and has durometer hardness in the range of about 50 A to about 90 A. The second catheter section is connected to the first section and has durometer hardness in the range of about 5 A to about 49 A. A selectively collapsible, substantially spherical retention balloon is attached coaxially and exterior of the first catheter section such that the proximal-most end of the retention balloon is coincident to the proximal-most end of the first section of the waste collection catheter, the substantially spherical retention balloon having an inflated size so as to be sufficiently large enough to retain the patient proximal end of the catheter in the patient's rectum without being so large as to trigger a defecatory response in the patient.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: A fecal diverting device includes an internal balloon formed at the inside of a tubular body part disposed at the front end of a connection tube, at least one external balloon formed at the outside of the tubular body part, and an enema liquid injection hole formed through the forefront of the tubular body part, so as to allow fillers to be respectively injected into the internal balloon and the at least one external balloon and an enema liquid to be injected into an intestinal tract of a patient via an enema liquid injection hole through a control tube; and a device controller connected to the control tube for regulating the amounts of the fillers filling the internal balloon and the at least one external balloon through the control tube based on a predetermined fecal diverting program, and controlling the injection of the enema liquid, supplied from an enema liquid supplying unit, into the intestinal tract via the enema liquid injection hole through the control tube.

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a lower semiconductor substrate, an upper semiconductor pattern on the lower semiconductor substrate, a device isolation pattern defining an active region in the lower semiconductor substrate and the upper semiconductor pattern, a lower charge storage layer between the upper semiconductor pattern and the lower semiconductor substrate, a gate conductive structure crossing over the upper semiconductor pattern, a first upper charge storage layer and a second upper charge storage layer spaced apart from each other between the gate conductive structure and the upper semiconductor pattern, and a source/drain region in the upper semiconductor pattern on both sides of the gate conductive structure.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate are disposed on the tunnel insulation layer. An isolation gate is disposed between the first and second memory gates. A word line covers the first memory gate, the second memory gate and the isolation gate. A method of forming the nonvolatile memory device is also provided.

Abstract: A method for fabricating a memory cell includes forming a stacked insulating layer, and a lower conductive layer on a semiconductor substrate, patterning the lower conductive layer and the insulating layer to form a gap region, forming a gate insulating layer on exposed surfaces of the semiconductor substrate and the lower conductive layer in the gap region, forming a gate pattern on the gate insulating layer for filling the gap region, the gate pattern protruded upward to have sidewall portions exposed above the lower conductive layer, forming an upper sidewall pattern on each exposed sidewall portion of the gate pattern, patterning the lower conductive layer and the insulating layer to form a lower sidewall pattern and a charge storage layer under each upper sidewall pattern, wherein the gate pattern and each upper sidewall pattern are used as an etching mask.

Abstract: An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

Abstract: A monitor apparatus for a laparoscopic surgery rotates images captured by a laparoscope as an endoscope and displayed on monitors for the laparoscopic surgery clockwise or counter-clockwise according to commands for rotating the images by surgeons who use image rotation manipulation parts such that the images of surgical devices displayed on the monitors are arranged in the direction where the surgeons can actually manipulate the laparoscopic surgical devices most conveniently.

Abstract: An EEPROM device is provided with an active region including a first region, a second region having a lower top surface than a top surface of the first region, and a sidewall disposed at the boundary between the first and second regions. A tunneling region of charges for a program operation and/or an erase operation is defined within the sidewall.

Abstract: A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate.

Abstract: A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate.

Abstract: A tunneling dielectric layer, a charge trapping layer, a first length defining layer, and a second length defining layer are sequentially deposited on a semiconductor substrate. These layers are sequentially patterned. Exposed both sidewalls of the first length defining layer first pattern are recessed by selective side etching. After forming a blocking layer for covering the exposed charge trapping layer and a gate layer for filling the recessed portion, the gate layer is patterned to form spacer shaped gates. Dopant regions for source and drain regions are formed on the semiconductor substrate adjacent the gates.

Abstract: In a non-volatile memory device and methods of forming and operating the same, one memory transistor includes sidewall selection gates covering both sidewalls of a floating gate when the floating gate and a control gate are stacked. The sidewall selection gates are in a spacer form. Since the sidewall selection gates are in a spacer form on the sidewall of the floating gate, the degree of integration of cells can be improved. Additionally, since the side wall selection gates are disposed on both sidewalls of the floating gate, a voltage applied from a bit line and a common source line can be controlled and thus conventional writing/erasing errors can be prevented. Therefore, distribution of threshold voltage can be improved.

Abstract: A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and drain regions. Charge storage layers are formed the channel region. A gate insulating layer is formed on the channel region between the charge storage layers, and a gate electrode is formed on the gate insulating layer and the charge trapping storage layers.