Patents by Inventor Jae-Hyun Han

Jae-Hyun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250040296
    Abstract: A semiconductor nanoparticle, a method of preparing the semiconductor nanoparticle, and an electroluminescent device including the semiconductor nanoparticle. The method of preparing the semiconductor nanoparticle includes contacting a zinc precursor and a sulfur precursor in the presence of a first particle at a predetermined temperature to form a semiconductor nanocrystal layer containing zinc sulfide on the first particle, wherein the first particle includes a Group II-VI compound including zinc, selenium, and, optionally, tellurium, or the first particle includes a Group III-V compound including indium and phosphorus. The predetermined temperature includes (e.g., is) a temperature (e.g., a reaction temperature) of greater than 300° C. and less than or equal to about 380° C., and the sulfur precursor includes a thiol compound of C3 (e.g. C9) to C50 or a combination thereof.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 30, 2025
    Inventors: Ji Hyun MIN, DAEUN YOON, Won Sik YOON, Jae Yong LEE, Hogeun CHANG, Hyundong HA, Yong Seok HAN
  • Patent number: 12207572
    Abstract: An electronic device includes a base element, a source electrode layer and a drain electrode layer disposed to be spaced apart from each other on the base element, a channel layer disposed between the source electrode layer and the drain electrode layer on the base element that accommodates metal ions, a metal ion conduction layer disposed on the channel layer, and a gate electrode layer disposed on the metal ion conduction layer. The channel layer includes a plurality of unit films and channel spaces between the plurality of unit films. The plurality of unit films are arranged to be parallel to a direction substantially perpendicular to a surface of the base element.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: January 21, 2025
    Assignee: SK hynix Inc.
    Inventors: Won Tae Koo, Jae Hyun Han
  • Patent number: 12206972
    Abstract: According to an embodiment of the present invention, disclosed is a camera apparatus comprising: a substrate; a light emitting part; a light receiving part comprising an image sensor located on the substrate; and a controller that controls the optical part or the light source using an output value received from a photodetector, wherein the light emitting part comprises: a light source located on the substrate; a holder located on the substrate; an optical part located on the light source; a driving part that moves the optical part along an optical axis; and the photodetector located on the substrate.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: January 21, 2025
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Heon Han, Bum Jin Kim, Seok Hyun Kim, In Jun Seo, Myung Jin Song, Jae Hoon Lee
  • Publication number: 20250022784
    Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
  • Patent number: 12201040
    Abstract: An electronic device includes a substrate, a source electrode layer and a drain electrode layer that are disposed to be spaced apart from each other over the substrate, a channel layer that is capable of receiving hydrogen, disposed between the source electrode layer and the drain electrode layer over the substrate, a proton conductive layer disposed on the channel layer, a hydrogen source layer disposed on the proton conductive layer, and a gate electrode layer disposed on the hydrogen source layer.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: January 14, 2025
    Assignee: SK hynix Inc.
    Inventors: Won Tae Koo, Jae Hyun Han
  • Publication number: 20250003689
    Abstract: Provided are a connection tube and a condenser. The connection tube includes: multi-row tubes respectively connecting a flow path between a pair of header pipe assemblies disposed to be spaced apart from each other and including a plurality of header pipes disposed to be parallel to each other in a second direction, perpendicular to a first direction which is a length direction of the header pipe having the flow path formed therein and a plurality of connection holes formed in one surface.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 2, 2025
    Inventors: Yong Beom PARK, Jae Hyun HAN
  • Publication number: 20240381655
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: SK hynix Inc.
    Inventors: Won Tae KOO, Jae Hyun HAN, Se Ho LEE
  • Publication number: 20240361078
    Abstract: A connection block facilitates connection between circular pipes with excellent fracture withstand pressure and has flow holes to allow fluid movement between pipes, a header connector connecting the connection block to a header pipe, and a condenser including of the same and a plurality of connection tubes in a plurality of rows. The connection block includes a first surface, a second surface spaced apart from the first surface, a pair of curved portions connecting ends of the first surface and ends of the second surface, and a plurality of flow holes penetrating through the curved portions, wherein the pair of curved portions have the same curvature in cross section, perpendicular to a longitudinal direction.
    Type: Application
    Filed: August 19, 2022
    Publication date: October 31, 2024
    Inventors: Kyeong-Sik YOU, Young-Hyun KIM, Jae-Hyun HAN, Myoung-Seop LEE, Moon-Yong PARK, Chul-Ki JEONG, Wang-Yun KIM
  • Publication number: 20240357836
    Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Jae Hyun HAN, Se Ho LEE, Hyangkeun YOO
  • Publication number: 20240353593
    Abstract: Provided are an optical member and an optical display device comprising same, the optical member comprising a support layer and an optically functional layer laminated on one surface of the support layer, wherein: the optically functional layer includes a groove having inclined surfaces; at least one convex portion extending from the flat portion of the optically functional layer is formed at each of the inclined surfaces; the convex portion is a curved surface with a radius of curvature of 1 mm or greater, and each of the inclined surfaces satisfies expression 1.
    Type: Application
    Filed: August 3, 2022
    Publication date: October 24, 2024
    Inventors: Kyoung Gon PARK, Sung Hyun MUN, Jin Young LEE, Ji Young HAN, Ji Won KANG, Ji Yeon KIM, Ji Ho KIM, Jae Hyun HAN, Il Jin KIM, Gwang Hwan LEE, Do Young KIM, Dong Myeong SHING
  • Publication number: 20240327684
    Abstract: An adhesive film and a display member including the same are disclosed. The adhesive film is formed of an adhesive composition including: a copolymer of a monomer mixture including a hydroxyl group-containing (meth)acrylate and a comonomer; and nanoparticles. The adhesive film has a creep at ?20° C. of about 50 ?m to about 100 ?m and a gel fraction of about 50% to about 75%.
    Type: Application
    Filed: June 3, 2024
    Publication date: October 3, 2024
    Inventors: Ik Hwan Cho, Ji Ho Kim, Jee Hee Kim, Ji Won Kang, Byeong Do Kwak, Yong Tae Kim, Il Jin Kim, Sung Hyun Mun, Hyung Rang Moon, Seon Hee Shin, Gwang Hwan Lee, Woo Jin Lee, Jae Hyun Han
  • Patent number: 12108611
    Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: October 1, 2024
    Assignee: SK HYNIX INC.
    Inventors: Jae Hyun Han, Se Ho Lee, Hyangkeun Yoo
  • Patent number: 12108606
    Abstract: A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: October 1, 2024
    Assignee: SK hynix inc.
    Inventors: Jae Hyun Han, Jae Gil Lee, Hyangkeun Yoo, Se Ho Lee
  • Publication number: 20240313073
    Abstract: A semiconductor memory device includes a channel layer, a gate electrode spaced apart from the channel layer, a blocking insulating layer between the gate electrode and the channel layer, a tunnel insulating layer between the channel layer and the blocking insulating layer, and nano-particles spaced apart from each other between the tunnel insulating layer and the blocking insulating layer.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 19, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Hyun HAN, Won Tae KOO
  • Patent number: 12084605
    Abstract: An adhesive film formed of an adhesive composition including a (meth)acrylic copolymer including an alkylene glycol group and a cyclic functional group while satisfying Equation 3 and Equation 4 herein, an optical member including the same, and an optical display including the same, are provided.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 10, 2024
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Ji Ho Kim, Ji Won Kang, Il Jin Kim, Sung Hyun Mun, Kyoung Gon Park, Gwang Hwan Lee, Jin Young Lee, Jae Hyun Han
  • Patent number: 12082420
    Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: September 3, 2024
    Assignee: SK hynix Inc.
    Inventors: Won Tae Koo, Jae Hyun Han, Se Ho Lee
  • Patent number: 12072438
    Abstract: The present disclosure relates to a device and method for detecting vertical misalignment of a vehicle radar device and vehicle radar device with the same. A radar device according to an embodiment determines a monitoring range including the ground in front by using the radar signal, determines an error of vertical angles for a number of ground distances within the monitoring range, and detects the vertical mounting misalignment of the radar device by using the error. According to embodiments, it is possible to accurately determine the vertical mounting misalignment of the radar device even if there is a road surface non-uniformity, road slope, or radar beam width change.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: August 27, 2024
    Assignee: HL KLEMOVE CORP.
    Inventors: Han Byul Lee, Ho Young Jin, Jae Hyun Han, Jung Hwan Choi, Jingu Lee
  • Patent number: 12063795
    Abstract: A semiconductor device includes a substrate, a first bit line disposed on the substrate, a first tunnel insulation layer disposed on the first bit line, a variable resistance structure disposed on the first tunnel insulation layer and having a pillar structure, a second tunnel insulation layer disposed on an upper surface of the variable resistance structure, a second bit line disposed on the second tunnel insulation layer, a barrier insulation layer disposed on a sidewall surface of the variable resistance structure, and a word line disposed on the barrier insulation layer. A dielectric constant of the barrier insulation layer is greater than a dielectric constant of each of the first and second tunnel insulation layers.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: August 13, 2024
    Assignee: SK HYNIX INC.
    Inventor: Jae Hyun Han
  • Publication number: 20240244826
    Abstract: A semiconductor device includes a substrate, a bit line conductive layer extending in a lateral direction substantially parallel to a surface of the substrate, a first insulation line structure extending in a second direction that is perpendicular to the first lateral direction and that is substantially parallel to the surface of the substrate, first and second channel structures that are disposed to respectively contact first and second sides of the first insulation line structure and that partially overlap with the bit line conductive layer, first and second gate dielectric layers respectively disposed over the substrate and on side surfaces of the first and second channel structures, and first and second gate line conductive layers extending in the second lateral direction over the substrate and covering at least a portion of each of the first and second gate dielectric layers, respectively.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Jae Hyun HAN, Dong Ik SUH, Jae Gil LEE
  • Publication number: 20240200838
    Abstract: An evaporative condenser includes N header rows including a first header extending in a first direction and having a flow path therein, a second header extending in the first direction and having a flow path therein, and a plurality of connecting tubes extending in a second direction between the first header and the second header and connecting the flow paths of the first header and the second header, the N header rows being stacked in a third direction, where N is a natural number greater than or equal to 2. The first to third directions are directions orthogonal to each other, the connecting tube of one header row is spaced apart from the connecting tube of an adjacent header row by a first distance, a fin member providing a flow path in the third direction is disposed between the connecting tubes.
    Type: Application
    Filed: October 4, 2023
    Publication date: June 20, 2024
    Inventors: Jae Hyun HAN, Myoung Seop LEE, Chul Ki JEONG