Abstract: A semiconductor device including at least one variable resistance device is provided. A variable resistance element includes: an ion supply layer having a top, a bottom and a sidewall connecting the top to the bottom; an ion-receiving layer having an inner sidewall connected to at least a portion of the sidewall of the ion supply layer; a gate pattern connected to an outer sidewall of the ion-receiving layer; and a source pattern connected to one of the top or bottom of the ion supply layer, and a drain pattern connected to the other one or the top or bottom of the ion supply layer. A resistance of the ion supply layer is varies depending on an amount of ions supplied from the ion supply layer to the ion-receiving layer in response to a voltage applied to the gate pattern.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, and a gate structure disposed on the substrate and including a hole pattern. The gate structure includes at least one gate electrode layer and at least one interlayer insulation layer which are alternately stacked, and the gate electrode layer protrudes toward a center of the hole pattern relative to the interlayer insulation layer. The nonvolatile memory device includes a first functional layer disposed along a sidewall surface of the gate structure inside the hole pattern, a second functional layer disposed on the first functional layer inside the hole pattern, and a channel layer extending in a direction perpendicular to the substrate inside the hole pattern and disposed to contact a cell portion of the second functional layer. The cell portion of the second functional layer indirectly covers a sidewall surface of the gate electrode layer.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

Abstract: An adhesive film and a display member, the adhesive film being formed of an adhesive composition that includes a monomer mixture comprising a hydroxyl group-containing (meth)acrylate and a comonomer, wherein the adhesive film has a recovery rate of about 40% to about 99%, the recovery rate being determined according to Method A as described herein, and wherein the adhesive film has a bubble generation area of about 0%, the bubble generation area being determined according to Method B as described herein.

Abstract: An adhesive film has an average slope of about ?9.9 to about 0, as measured over a temperature range of about ?20° C. to about 80° C. in a graph depicting a temperature-dependent storage modulus distribution of the adhesive film where the x-axis represents temperature (° C.) and the y-axis represents storage modulus (kPa). The adhesive film also has a storage modulus at about 80° C. of about 10 kPa to about 1,000 kPa.

Abstract: A semiconductor device includes a substrate, a plurality of word line structures disposed over the substrate to be spaced apart from each other in a first direction perpendicular to a surface of the substrate. Each of the plurality of word line structures extends in a second direction parallel to the surface of the substrate. In addition, the semiconductor device includes a switching layer disposed over the substrate to contact side surfaces of the plurality of word line structures, and bit line structures disposed over the substrate to extend in the first direction and to contact a surface of the switching layer. The switching layer is configured to perform a threshold switching operation, and has a variable programmable threshold voltage.

Abstract: A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulating layer that are alternately stacked over the substrate. The semiconductor device includes a hole pattern penetrating the gate structure over the substrate, and a gate insulating layer, a channel layer, a resistor layer, and a resistance changing layer sequentially disposed on a sidewall surface of the gate structure within the hole pattern. Each of the resistor layer and the resistance changing layer is disposed opposite to the gate insulating layer, based on the channel layer.

Abstract: The disclosure relates to a radar device and a control method. Specifically, according to the disclosure, a radar device comprises a transmitter controlling to transmit a frequency-modulated transmission signal, a receiver receiving a reception signal which is the transmitted transmission signal reflected by an object, an angle estimator estimating a first angle for a position of the object, with respect to a host vehicle, during one frame, based on a result obtained by performing fast Fourier transform (FFT) on the reception signal and estimating a second angle which is a virtual angle for the position of the object during a plurality of frames, and a controller calibrating the first angle by comparing the estimated first angle and the estimated second angle.

Abstract: A semiconductor device includes a substrate, a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate, first and second channel structures disposed on the bit line conductive layer to be spaced apart from each other in the first lateral direction, first and second gate dielectric layers disposed on side surfaces of the first and second channel structures over the substrate, first and second gate line conductive layers disposed on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers common to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate, and first and second storage node electrode layers disposed over the first and second channel structures, respectively.

Abstract: A nonvolatile memory device includes a substrate having an upper surface and a channel structure disposed over the substrate. The channel structure includes at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and the channel structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure, a gate insulation layer disposed over the substrate and on the resistance change layer, and a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer and disposed to be spaced apart from each other in the second direction.

Abstract: There are provided a variable resistance memory device and a manufacturing method of the same. The variable resistance memory device includes: a first electrode; a second electrode arranged in a vertical direction from the first electrode; and an oxide layer having an oxygen deficient region extending in the vertical direction between the second electrode and the first electrode.

Abstract: Provided herein may be a method of operating a semiconductor device including memory cells each storing multi-bit data. The method includes receiving data that is to be programmed in a memory cell selected from the memory cells; and applying a program pulse to the selected memory cell, the program pulse being determined depending on a logic state of the data and being selected from a group including a first program pulse having a positive polarity, a second program pulse having the positive polarity and having at least one of a peak level, a peak period, and a falling slew rate different from those of the first program pulse, a third program pulse having a negative polarity, and a fourth program pulse having the negative polarity and having at least one of a peak level, a peak period, and a rising slew rate different from those of the third program pulse.

Abstract: A memory cell includes a first electrode, a second electrode, a variable resistance layer located between the first electrode and the second electrode, and a ferroelectric layer located between the variable resistance layer and the second electrode, wherein the variable resistance layer is maintained in an amorphous state during a program operation.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack including word lines, a bit line penetrating the stack, a global bit line disposed above the stack, global word lines disposed above the stack, a common select line disposed above the stack, a first contact plug coupling the global bit line and the bit line to each other and penetrating the common select line, and second contact plugs coupling the global word lines and the word lines to each other respectively and penetrating the common select line.

Abstract: The present disclosure relates to a control apparatus and a control method of an adaptive cruise control system.

Abstract: A semiconductor device includes: a first bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; a second capacitor electrically isolated from the first transistor, the second capacitor being located at a second part of the first intersection; and a second transistor electrically connected to the second capacitor, the first capacitor and the second capacitor being located between the first transistor and the second transistor.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers (where N is a natural number of two or more) disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers includes a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the conductive lines of the first to Nth layers and the insulating layer therebetween; a variable resistance layer disposed on the sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed.

Abstract: A light source driving device may include a DC-DC conversion unit for generating an output voltage by adjusting a level of an input voltage, and a first light-emitting unit and a second light-emitting unit, which are driven by the output voltage of the DC-DC conversion unit. A regulator may be connected to the output end of the second light-emitting unit, and a controller may have a feedback terminal connected to the output ends of the first light-emitting unit and the second light-emitting unit. The regulator may operate such that a preset target current is supplied to the second light-emitting unit. The controller may adjust a duty of the pulse control signal based on the entire preset target current of the first light-emitting unit and the second light-emitting unit and the feedback current inputted through the feedback terminal.

Abstract: Provided is a voice sensor comprising a piezoelectric material layer includes a substrate, a support layer, a metal layer, a piezoelectric material layer on the metal layer and an electrode on the piezoelectric material layer, and the substrate integrally supports a device layer of the voice sensor by exposing a part of a thin film including the piezoelectric material layer, the electrode and a polymer layer.

Abstract: The present disclosure relates to a device and method for detecting vertical misalignment of a vehicle radar device and vehicle radar device with the same. A radar device according to an embodiment determines a monitoring range including the ground in front by using the radar signal, determines an error of vertical angles for a number of ground distances within the monitoring range, and detects the vertical mounting misalignment of the radar device by using the error. According to embodiments, it is possible to accurately determine the vertical mounting misalignment of the radar device even if there is a road surface non-uniformity, road slope, or radar beam width change.