Patents by Inventor Jae Hyun Son

Jae Hyun Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130001779
    Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 3, 2013
    Applicant: SK HYNIX INC.
    Inventors: Tae Min KANG, You Kyung HWANG, Jae-hyun SON, Dae Woong LEE, Byoung Do LEE, Yu Hwan KIM
  • Patent number: 8288873
    Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Min Kang, You Kyung Hwang, Jae-hyun Son, Dae Woong Lee, Byoung Do Lee, Yu Hwan Kim
  • Publication number: 20120154020
    Abstract: A stack package having stacked chips includes first voltage dropping units respectively formed in the chips; second voltage dropping units respectively formed in the chips; first signal generation units connected in parallel to a first line formed by connecting the first voltage dropping units in series, respectively formed in the chips, and configured to apply high level signals according to a voltage of the first line; second signal generation units connected in parallel to a second line formed by connecting in series the second voltage dropping units, respectively formed in the chips, and configured to apply high level signals according to a voltage of the second line; and chip selection signal generation units respectively formed in the chips, and configured to combine signals outputted from the first signal generation units and the second signal generation units and generate chip selection signals.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 21, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Dae Woong LEE, Yu Gyeong HWANG, Jae Hyun SON, Tae Min KANG, Chul Keun YOON, Byoung Do LEE, Yu Hwan KIM
  • Patent number: 8164200
    Abstract: A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Min Kang, You Kyung Hwang, Jae-hyun Son, Dae Woong Lee, Chul Keun Yoon, Byoung Do Lee, Yu Hwan Kim
  • Patent number: 8044301
    Abstract: A printed circuit board includes a lower plate provided with an internal circuit wiring and having a recessed part at a surface thereof and a plurality of projection patterns at a lower surface of the recessed part; an upper plate having the same structure of the lower plate and adhered to the lower plate so that surfaces formed with the recessed part are opposite to each other; a heat circulation medium injected into an internal space formed by the recessed parts of the lower and upper plates.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae Hyun Son
  • Publication number: 20110254167
    Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.
    Type: Application
    Filed: July 16, 2010
    Publication date: October 20, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Tae Min KANG, You Kyung HWANG, Jae-hyun SON, Dae Woong LEE, Byoung Do LEE, Yu Hwan KIM
  • Publication number: 20110121454
    Abstract: A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members.
    Type: Application
    Filed: July 13, 2010
    Publication date: May 26, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Tae Min KANG, You Kyung HWANG, Jae-hyun SON, Dae Woong LEE, Chul Keun YOON, Byoung Do LEE, Yu Hwan KIM
  • Publication number: 20100320348
    Abstract: An opener and a buffer table for a test handler are disclosed. The opener includes an opening plate, a plurality of pin blocks forming pairs, and at least one or more interval retaining apparatus for retaining an interval between the pin blocks forming a pair. Each of the pin blocks is movably coupled to the opening plate, and includes opening pins for releasing a holding state of a holding apparatus that holds semiconductor devices in a carrier board. Although semiconductor devices to be tested are altered in size and a carrier board loading with the semiconductor devices is thus replaced, the opener does not need to be replaced, thereby reducing the replacement cost and the waste of resources.
    Type: Application
    Filed: July 2, 2008
    Publication date: December 23, 2010
    Applicant: TECHWING., CO. LTD
    Inventors: Yun-Sung Na, In-Gu Jeon, Seung-Chul Ahn, Dong-Han Kim, Jae-Hyun Son
  • Publication number: 20090065187
    Abstract: A cooling unit for a semiconductor module includes a plate shaped first cooling body, a plate shaped second cooling body opposing the first cooling body and an adjustable cooling member placed between the first and second cooling bodies so that a distance between the first and second cooling bodies may be adjusted. Shapes of the cooling body include a honeycomb structure, cylinders, a hemicylindrical shape, a zigzag shape, and a bellows structure shape. By forming the cooling unit with an adjustable cooling member, the cooling unit can fit electronic devices of various sizes.
    Type: Application
    Filed: October 5, 2007
    Publication date: March 12, 2009
    Inventor: Jae Hyun SON
  • Publication number: 20080286531
    Abstract: A printed circuit board includes a lower plate provided with an internal circuit wiring and having a recessed part at a surface thereof and a plurality of projection patterns at a lower surface of the recessed part; an upper plate having the same structure of the lower plate and adhered to the lower plate so that surfaces formed with the recessed part are opposite to each other; a heat circulation medium injected into an internal space formed by the recessed parts of the lower and upper plates.
    Type: Application
    Filed: July 12, 2007
    Publication date: November 20, 2008
    Inventor: Jae Hyun SON