Patents by Inventor Jae-Hyung Park

Jae-Hyung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12016175
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate including an element isolation film and an active region defined by the element isolation film; a word line crossing the active region in a first direction; and a bit line structure on the substrate and connected to the active region, the bit line structure extending in a second direction crossing the first direction, wherein the bit line structure includes a first cell interconnection film including an amorphous material or ruthenium, a second cell interconnection film on and extending along the first cell interconnection film and including ruthenium, and a cell capping film on and extending along the second cell interconnection film.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: June 18, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Young Lee, Do Hyung Kim, Taek Jung Kim, Seung Jong Park, Jae Wha Park, Youn Jae Cho
  • Patent number: 12011520
    Abstract: Proposed is an indoor quarantine system using an individual mask. The indoor quarantine system may include: an indoor headcount checking device including a headcount checking unit configured to check the number of persons who stay in an indoor space and a headcount providing unit configured to provide headcount information checked by the headcount checking unit to mobile terminals of indoor users; and a disinfection mask worn on an indoor user and activating a disinfection function in accordance with a disinfection command based on the indoor headcount information received from the mobile terminal of the indoor user to disinfect harmful substances around the indoor user.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: June 18, 2024
    Inventor: Jae Hyung Park
  • Publication number: 20240194241
    Abstract: Disclosed herein is an apparatus for adjusting a reference voltage. The apparatus may include a gate signal generation unit for generating an RDQS gate signal, a reference voltage generation unit for setting a reference voltage based on the RDQS gate signal, and a reset counter for holding a voltage at the time at which the RDQS gate signal becomes low when the RDQS gate signal is not applied to the reference voltage generation unit for a specific time period.
    Type: Application
    Filed: July 18, 2023
    Publication date: June 13, 2024
    Inventors: Young-Deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO, Jae-Woong CHOI
  • Publication number: 20240195399
    Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
    Type: Application
    Filed: July 18, 2023
    Publication date: June 13, 2024
    Inventors: Yi-Gyeong KIM, Young-Su KWON, Su-Jin PARK, Young-Deuk JEON, Min-Hyung CHO, Jae-Woong CHOI
  • Publication number: 20240163139
    Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Young-deuk JEON, Young-Su KWON, Yi-Gyeong KIM, Su-Jin PARK, Min-Hyung CHO, Jae-Woong CHOI
  • Patent number: 11983248
    Abstract: Disclosed herein are an apparatus and method for classifying clothing attributes based on deep learning. The apparatus includes memory for storing at least one program and a processor for executing the program, wherein the program includes a first classification unit for outputting a first classification result for one or more attributes of clothing worn by a person included in an input image, a mask generation unit for outputting a mask tensor in which multiple mask layers respectively corresponding to principal part regions obtained by segmenting a body of the person included in the input image are stacked, a second classification unit for outputting a second classification result for the one or more attributes of the clothing by applying the mask tensor, and a final classification unit for determining and outputting a final classification result for the input image based on the first classification result and the second classification result.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: May 14, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chan-Kyu Park, Do-Hyung Kim, Jae-Hong Kim, Jae-Yeon Lee, Min-Su Jang
  • Patent number: 11969397
    Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 30, 2024
    Assignee: THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Mi-La Cho, Dong-Yun Shin, Jong-Young Choi, Chul-Woo Yang, Sung-Hwan Park, Seon-Yeong Lee, Min-Jung Park, Joo-Yeon Jhun, Se-Young Kim, Hyeon-Beom Seo, Jae-Yoon Ryu, Keun-Hyung Cho
  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Publication number: 20240117052
    Abstract: Disclosed is an antibody for cancer treatment conjugated with a tumor environment-sensitive cleavable polyethylene glycol, wherein the use of the antibody for cancer treatment can suppress side effects of the antibody while maintaining therapeutic effects thereof.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Jae Hyung PARK, Seok Ho SONG, Torsha GHOSH
  • Patent number: 11952490
    Abstract: The present disclosure relates to a polycarbonate resin composition, and more particularly, to a polycarbonate resin composition containing 90 wt % to 99 wt % of a polycarbonate resin, 0.3 wt % to 0.7 wt % of an anthraquinone-based black dye, and 0.2 wt % to 1.0 wt % of an acrylic polymeric chain extender, and a molded article containing the same.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: April 9, 2024
    Assignees: HYUNDAI MOBIS CO., LTD., LG CHEM, LTD.
    Inventors: Hyoung Taek Kang, Keun Hyung Lee, Young Min Kim, Moo Seok Lee, Myeung Il Kim, Jae Chan Park
  • Patent number: 11948808
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 2, 2024
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Dong Jin Kim, Jin Han Kim, Won Chul Do, Jae Hun Bae, Won Myoung Ki, Dong Hoon Han, Do Hyung Kim, Ji Hun Lee, Jun Hwan Park, Seung Nam Son, Hyun Cho, Curtis Zwenger
  • Patent number: 11945744
    Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: April 2, 2024
    Assignees: SAMSUNG ENGINEERING CO., LTD., SAMSUNG ELECTRONICS CO., LTD
    Inventors: Seok Hwan Hong, Dae Soo Park, Seung Joon Chung, Yong Xun Jin, Jae Hyung Park, Jae Hoon Choi, Jae Dong Hwang, Jong Keun Yi, Su Hyoung Cho, Kyu Won Hwang, June Yurl Hur, Je Hun Kim, Ji Won Chun
  • Publication number: 20240099071
    Abstract: A display device includes a first substrate, a first electrode above the first substrate, a pixel-defining film above the first electrode, and defining an emission area, a light-emitting layer above the first electrode and the pixel-defining film, a second electrode above the light-emitting layer, a thin-film encapsulation structure above the second electrode, and including an organic film defining an opening, and a color control layer above the thin-film encapsulation structure in the opening.
    Type: Application
    Filed: June 23, 2023
    Publication date: March 21, 2024
    Inventors: Sang Hyung LIM, Se Jin PARK, Jae Ho EO, Soon Mi CHOI
  • Patent number: 11937440
    Abstract: The present invention may provide an organic electroluminescent device which exhibits low driving voltage as well as high efficiency by including an electron transporting layer material having an improved electron transporting ability.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: March 19, 2024
    Assignee: SOLUS ADVANCED MATERIALS CO., LTD.
    Inventors: Song Ie Han, Min Sik Eum, Jae Yi Sim, Yong Hwan Lee, Woo Jae Park, Tae Hyung Kim
  • Patent number: 11919351
    Abstract: A vehicle height control apparatus includes an information acquisition device that acquires pressure data on a pressure inside an air tank storing compressed air and obstacle data on an obstacle in front of a vehicle, and a controller that calculates a target vehicle height based on the obstacle data, calculates a required distance required to reach the target vehicle height based on the pressure of the compressed air inside the air tank, and determines a vehicle height control timing, resolving a problem that the vehicle height is unnecessarily quickly controlled compared to the position of the obstacle, or is controlled after the vehicle passes through the obstacle to reduce the ride comfort.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 5, 2024
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Jae Hyung Park, Woo Sung Lee, Eun Woo Na
  • Patent number: 11916535
    Abstract: Devices and methods related to film bulk acoustic resonators. In some embodiments, a film bulk acoustic resonator can be manufactured by a method that includes forming a first electrode having a first lateral shape and providing a piezoelectric layer on the first electrode. The method can further include forming a second electrode having a second lateral shape on the piezoelectric layer such that the piezoelectric layer is between the first and second electrodes. The forming of the first electrode and the forming of the second electrode can include selecting and arranging the first and second lateral shapes to provide a resonator shape defined by an outline of an overlap of the first and second electrodes, such that the resonator shape includes N curved sections joined by N vertices of an N-sided polygon, and such that the resonator shape has no axis of symmetry.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: February 27, 2024
    Assignee: SKYWORKS GLOBAL PTE. LTD.
    Inventors: Jae Myoung Jhung, Jae Hyung Lee, Kwang Jae Shin, Myung Hyun Park
  • Publication number: 20240034658
    Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).
    Type: Application
    Filed: April 14, 2023
    Publication date: February 1, 2024
    Inventors: Seok Hwan HONG, Dae Soo PARK, Seung Joon CHUNG, Yong Xun JIN, Jae Hyung PARK, Jae Hoon CHOI, Jae Dong HWANG, Jong Keun YI, Su Hyoung CHO, Kyu Won HWANG, June Yurl HUR, Je Hun KIM, Ji Won CHUN
  • Patent number: 11810912
    Abstract: Power semiconductor devices comprise a gate pad, a plurality of gate fingers, and a first gate resistor and a first switch that are coupled between the gate pad and the gate fingers.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: November 7, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: In-Hwan Ji, Jae-Hyung Park, Edward Van Brunt
  • Publication number: 20230298631
    Abstract: A stacked semiconductor device includes at least one upper chip including a plurality of channels each including first and second pseudo-channels; and a plurality of transfer control circuits respectively corresponding to the channels and each configured to output channel commands according to a channel designation signal designating one of the first and second pseudo-channels and a location information signal indicating a location of a corresponding channel of the channels, and transmit first and second data words between the corresponding channel and a lower chip according to the channel commands.
    Type: Application
    Filed: August 10, 2022
    Publication date: September 21, 2023
    Inventors: Jae Hyung PARK, Seung Geun BAEK, Dong Uk LEE
  • Patent number: 11721755
    Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: August 8, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Philipp Steinmann, Edward Van Brunt, Jae Hyung Park, Vaishno Dasika