Abstract: A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal.

Abstract: Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level.

Abstract: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

Abstract: A pipe latch circuit includes a pipe input unit configured to receive a plurality of data in an order corresponding to address information, a control signal generator configured to generate first and second control clock signals by using the address information, where the first and second control clock signals correspond to a synchronization clock signal, and a pipe output unit configured to synchronize an output signal of the pipe input unit with the first and second control clock signals and output the synchronized output signal.

Abstract: A semiconductor memory device includes a first data input circuit configured to align data inputted to a first data pad in parallel for transferring the aligned data to a first global bus and for transferring the aligned data to a second global bus in a test mode; and a second data input circuit configured to align data inputted to a second data pad in parallel for transferring the aligned data to the second global bus and to not receive data in the test mode.

Abstract: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

Abstract: A clock path control circuit includes a clock control signal generating unit configured to generate a clock control signal having an activation period corresponding to an activation period of a data input buffer; and a clock transfer unit configured to provide a clock signal to a write clock path in response to the clock control signal during the activation period of the clock control signal.

Abstract: A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.

Abstract: Provided is a quantum dot-metal oxide complex including a quantum dot and a metal oxide forming a 3-dimensional network with the quantum dot. In the quantum dot-metal oxide complex, the quantum dot is optically stable without a change in emission wavelength band and its light-emitting performance is enhanced.

Abstract: There is provided a quantum dot wavelength converter including a quantum dot, which is optically stable without any change in an emission wavelength and improved in emission capability. The quantum dot wavelength converter includes: a wavelength converting part including a quantum dot wavelength-converting excitation light and generating a wavelength-converted light and a dispersive medium dispersing the quantum dot; and a sealer sealing the wavelength converting part.

Abstract: The present invention relates to a method for increasing the binding reversibility of a ?-conotoxin to a N-type calcium channel, which comprises preparing a ?-conotoxin having a Ile and/or Ala residue at a position of amino acid (11 and/or 12), respectively in the second loop between cysteine residues (2 and 3) of the ?-conotoxin represented by the formula I, such that the prepared ?-conotoxin has the increased binding reversibility to N-type calcium channel. In addition, the present invention relates to a novel ?-conotoxin and a pharmaceutical composition having plausible properties in view of blocking activity to and specificity to N-type calcium channel, and dramatically improved binding reversibility to N-type calcium channel.

Abstract: Provided is a wavelength conversion plate having excellent luminous efficiency of a wavelength-converted light. The wavelength conversion plate includes a dielectric layer with nano pattern, a metal layer formed inside the nano pattern, and a wavelength conversion layer formed on the metal layer and having quantum dot or phosphor which wavelength-converts an excitation light to generate a wavelength-converted light.

Abstract: A multi-port memory device includes a plurality of ports, a plurality of bank control units, a plurality of banks, a read clock generation unit, and a data transmission unit. Each of the banks is connected to a corresponding one of the bank control units. The read clock generation unit generates a read clock toggling for four clocks in response to a read command. The data transmission unit transmits a read data from the banks to a corresponding one of the ports in response to the read clock. Every bank control unit is connected to all of the ports.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

Abstract: The present invention relates to an indirubin derivative having anticancer property by inhibiting cell proliferation as to human cancer cell line. More particularly, this invention provides the synthesis of indirubin derivative known as CDK(Cyclin-dependent kinase) inhibitor. Further, inhibition activity of proliferation as to human cancer cell line and apoptosis against induced-differentiation of said indirubin derivative are researched to develop a novel indirubin derivative having efficacious anticancer properties as to various human cell lines.

Abstract: A fuse monitoring circuit for a semiconductor device includes a repair fuse unit including a number of fuses to which a repair address is programmed, and configured to output fuse state signals corresponding to the connection states of the respective fuses in response to a fuse initialization signal. A serial fuse monitoring unit is configured to output a fuse state monitoring signal corresponding to each fuse state signal selected by an applied address in response to a serial monitoring test mode signal. Also, a parallel fuse monitoring unit is configured to output a repair monitoring signal by comparing an applied address and the repair address in response to a parallel monitoring test mode signal. An output unit is configured to output the fuse state monitoring signal and the repair monitoring signal to an output pad in response to an output control signal.

Abstract: A test device that can improve test reliability is provided. In the test device, an error detecting unit detects an error of inputted test signals to generate an error flag, a normal test unit performs a test operation according to the test signals when the error flag is deactivated, and an error information providing unit indicates the error of the test signals when the error flag is activated.

Abstract: Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver.

Abstract: A multi-port memory device has a plurality of ports which are connected to different external devices with the memory device performing serial data communication independently. The memory device has a plurality of banks, each of which has a plurality of cell arrays. The memory device also has a write counter for increasing the counting number whenever write data are applied to the banks through the ports and a write data register for temporarily storing the write data according to the count number. A write flag signal generator generates a flag signal for writing the temporarily stored data to the banks. The memory device also has a write enable signal generator for generating a write enable signal is response to the flag signal to write the temporarily stored write data to the banks.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.