Abstract: A multi-port memory device has a plurality of ports which are connected to different external devices with the memory device performing serial data communication independently. The memory device has a plurality of banks, each of which has a plurality of cell arrays. The memory device also has a write counter for increasing the counting number whenever write data are applied to the banks through the ports and a write data register for temporarily storing the write data according to the count number. A write flag signal generator generates a flag signal for writing the temporarily stored data to the banks. The memory device also has a write enable signal generator for generating a write enable signal is response to the flag signal to write the temporarily stored write data to the banks.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

Abstract: A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.

Abstract: A semiconductor memory device is capable of reducing a test time upon the same condition of the actual operation thereof. The semiconductor memory device includes an output data select unit and a data output unit. The output data select unit selectively outputs valid data, which are loaded on a plurality of global lines, in response to an output control signal activated after a delay time corresponding to an additive latency from entry of a read operation in a test mode. The data output unit aligns data outputted from the output data select unit and outputs the aligned data through data pads.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

Abstract: Disclosed is a controller for driving current of a semiconductor device having an over-driving function, the controller comprising: a load means supplied with an internal voltage; a plurality of switching means, each of which has a first terminal connected to an external voltage and a second terminal connected to the load means, wherein at least one of the plurality of switching means is selectively turned on/off according to an voltage level of the external voltage.

Abstract: A multi-port memory device includes a plurality of ports, a plurality of bank control units, a plurality of banks, a read clock generation unit, and a data transmission unit. Each of the banks is connected to a corresponding one of the bank control units. The read clock generation unit generates a read clock toggling for four clocks in response to a read command. The data transmission unit transmits a read data from the banks to a corresponding one of the ports in response to the read clock. Every bank control unit is connected to all of the ports.

Abstract: A multi-port memory device including a plurality of ports, a plurality of banks and a plurality of bank controllers, wherein all of the bank controllers share all of the ports, the device includes a phase locked loop (PLL) unit for generating an internal clock signal; a delay unit, provided in each bank controller, for generating first and second delayed clock signals by delaying the internal clock signal; a serializer, provided in each bank controller, for receiving a plurality of parallel data from all of the ports and fitting the parallel data for a corresponding data frame in response to the first delayed clock signal; and a command decoder, provided in each bank controller, for decoding output data of the serializer to generate command signals in response to the second delayed clock signal.

Abstract: A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.

Abstract: The present invention relates to a method for synthesizing high luminescence semiconductor quantum dots with a core-shell structure in a short time in large quantity. Using the method of synthesizing the quantum dots in accordance with the present invention, a large quantity of quantum dots can be economically synthesized in a rapid time without an explosion. And, the present invention can be applied to the fields employing various luminous materials since the luminous semiconductor quantum dots synthesized by the present invention has a high luminous efficiency and they can emit a light at various wavelengths in the whole range of a visible ray. And also, the present invention can be applied to a light emission device, a single electron transistor, a solar cell photo-sensitizer material and a bio-labelling tag since it is excellently stable.

Abstract: A novel phosphorescent material containing an iridium metal compound and an organic electroluminescent device using the same are provided. When used for an emissive layer of an organic electroluminescent device, the phosphorescent material offers greater luminescent efficiency and improved driving voltage characteristics, compared to conventional red luminescent materials, and reduces the amount of power consumed in the organic electroluminescent device.

Abstract: Disclosed is a fluorine compound having perfluorostyrene introduced at a terminal thereof, as represented in the following Formula 1, and a coating solution and an optical waveguide device using the same, characterized in that the introduction of perfluorostyrene results in a facile fabrication of thin films by a UV curing or a thermal curing, high thermal stability and chemical resistance, and low optical propagation loss and birefringence: Wherein Z is O or S; RF is an aliphatic or aromatic group; y is a natural number of 1-10; y? is an integer of 0-1, x is an integer of 0-200; and Wherein B is a single bond or selected from the group consisting of —CO—, —SO2—, —S— and —O—, and Hal is selected from the group consisting of F, Cl, Br and I.

Abstract: The present invention relates to an indirubin derivative having anticancer property by inhibiting cell proliferation as to human cancer cell line. More particularly, this invention provides the synthesis of indirubin derivative known as CDK(Cyclin-dependent kinase) inhibitor. Further, inhibition activity of proliferation as to human cancer cell line and apoptosis against induced-differentiation of said indirubin derivative are researched to develop a novel indirubin derivative having efficacious anticancer properties as to various human cell lines.

Abstract: A test device that can improve test reliability is provided. In the test device, an error detecting unit detects an error of inputted test signals to generate an error flag, a normal test unit performs a test operation according to the test signals when the error flag is deactivated, and an error information providing unit indicates the error of the test signals when the error flag is activated.

Abstract: A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

Abstract: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

Abstract: Disclosed is a method for providing an accident broadcasting guidance service of an accident broadcasting guidance system connected to mobile communication terminals. The method includes when an accident has occurred, generating a view-recommendation message of an accident broadcasting sent from a broadcasting station; and transmitting the view-recommendation message to mobile communication terminals within an area in which the accident has occurred. In the method, a view-recommendation message of an accident broadcasting is transmitted to a mobile communication terminal within an area in which the accident has occurred, so that the accident broadcasting can be automatically received in the mobile communication terminal. Accordingly, a user can quickly cope with the urgent accident, which can reduce casualties involving person and property and contribute to convenience of users.

Abstract: A multi-port memory device having a plurality of ports which are connected to different external devices and perform a serial data communication independently, and a plurality of banks each having a plurality of cell arrays, includes a write counter for increasing a counting number whenever write data are applied to the banks through the ports; a write data register for temporarily storing the write data according to the count number; a write flag signal generator for generating a flag signal for writing the temporarily stored write data to the banks; and a write enable signal generator for generating a write enable signal in response to the flag signal to write the temporarily stored write data to the banks.

Abstract: Disclosed is a fluorine compound having perfluorostyrene introduced at a terminal thereof, as represented in the following Formula 1, and a coating solution and an optical waveguide device using the same, characterized in that the introduction of perfluorostyrene results in a facile fabrication of thin films by a UV curing or a thermal curing, high thermal stability and chemical resistance, and low optical propagation loss and birefringence: Wherein Z is O or S; RF is an aliphatic or aromatic group; y is a natural number of 1-10; y? is an integer of 0-1; x is an integer of 0-200; and Wherein B is a single bond or selected from the group consisting of —CO—, —SO2—, —S— and —O—, and Hal is selected from the group consisting of F, Cl, Br and I.

Abstract: Disclosed is a fluorine compound having perfluorostyrene introduced at a terminal thereof, as represented in the following Formula 1, and a coating solution and an optical waveguide device using the same, characterized in that the introduction of perfluorostyrene results in a facile fabrication of thin films by a UV curing or a thermal curing, high thermal stability and chemical resistance, and low optical propagation loss and birefringence: 1