Patents by Inventor Jae-Jong Han
Jae-Jong Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11069820Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: GrantFiled: April 14, 2020Date of Patent: July 20, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Gun Ho Jo, Dae Joung Kim, Jae Mun Kim, Moon Han Park, Tae Ho Cha, Jae Jong Han
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Publication number: 20200243398Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Gun Ho JO, Dae Joung KIM, Jae Mun KIM, Moon Han PARK, Tae Ho CHA, Jae Jong HAN
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Patent number: 10658249Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: GrantFiled: October 25, 2018Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Gun Ho Jo, Dae Joung Kim, Jae Mun Kim, Moon Han Park, Tae Ho Cha, Jae Jong Han
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Publication number: 20190148521Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.Type: ApplicationFiled: October 25, 2018Publication date: May 16, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Gun Ho JO, Dae Joung KIM, Jae Mun KIM, Moon Han PARK, Tae Ho CHA, Jae Jong HAN
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Patent number: 9859376Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.Type: GrantFiled: December 22, 2015Date of Patent: January 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Han-ki Lee, Jae-Young Park, Dong-Hun Lee, Bon-Young Koo, Sun-Young Lee, Jae-Jong Han
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Publication number: 20160293705Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.Type: ApplicationFiled: December 22, 2015Publication date: October 6, 2016Inventors: Han-ki Lee, Jae-Young Park, Dong-Hun Lee, Bon-Young Koo, Sun-Young Lee, Jae-Jong Han
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Patent number: 9390977Abstract: A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins.Type: GrantFiled: August 13, 2015Date of Patent: July 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jae Jong Han, Bon Young Koo, Ki Yeon Park, Jae Young Park, Sun Young Lee, Kyung In Choi
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Publication number: 20160086943Abstract: A semiconductor device includes a substrate, an isolation layer on the substrate, and at least one active fin on the substrate. The isolation layer includes a first surface opposite a second surface. The first surface is contiguous with the substrate. The at least one active fin protrudes from the substrate and includes a first region having a side wall above the second surface of the isolation layer and a second region on the first region. The second region has an upper surface. The first region has a first width contiguous with the second surface of the isolation layer and a second width contiguous with the second region. The second width is 60% or greater than the first width (e.g., 60% to 100%).Type: ApplicationFiled: September 17, 2015Publication date: March 24, 2016Inventors: Sun Young LEE, Jae Young Park, Han Ki Lee, Bon Young Koo, Hong Bum Park, Young Su Chung, Jae Jong Han
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Publication number: 20160049336Abstract: A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins.Type: ApplicationFiled: August 13, 2015Publication date: February 18, 2016Inventors: Jae Jong HAN, Bon Young KOO, Ki Yeon PARK, Jae Young PARK, Sun Young LEE, Kyung In CHOI
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Patent number: 9202844Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.Type: GrantFiled: August 14, 2013Date of Patent: December 1, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Jong Han, Yoon-Goo Kang, Won-Seok Yoo, Kong-Soo Lee, Han-Jin Lim, Seong-Hoon Jeong
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Patent number: 8987694Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.Type: GrantFiled: December 28, 2012Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Jong Han, Kong-Soo Lee, Yoon-Goo Kang, Ho-Kyun An, Seong-Hoon Jeong
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Publication number: 20140158964Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.Type: ApplicationFiled: August 14, 2013Publication date: June 12, 2014Inventors: Jae-Jong HAN, Yoon-Goo Kang, Won-Seok Yoo, Kong-Soo Lee, Han-Jin Lim, Seong-Hoon Jeong
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Patent number: 8497545Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: GrantFiled: January 7, 2011Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
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Method of forming a vertical diode and method of manufacturing a semiconductor device using the same
Patent number: 8241979Abstract: A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.Type: GrantFiled: August 20, 2010Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jin Park, Kong-Soo Lee, Yong-Woo Hyung, Young-Sub You, Jae-Jong Han -
Publication number: 20110101437Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: ApplicationFiled: January 7, 2011Publication date: May 5, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
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Patent number: 7888204Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: GrantFiled: August 15, 2008Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim
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Method of forming a vertical diode and method of manufacturing a semiconductor device using the same
Publication number: 20100323489Abstract: A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.Type: ApplicationFiled: August 20, 2010Publication date: December 23, 2010Inventors: Sang-Jin Park, Kong-Soo Lee, Yong-Woo Hyung, Young-Sub You, Jae-Jong Han -
Method of forming a vertical diode and method of manufacturing a semiconductor device using the same
Patent number: 7803679Abstract: A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.Type: GrantFiled: February 20, 2008Date of Patent: September 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jin Park, Kong-Soo Lee, Yong-Woo Hyung, Young-Sub You, Jae-Jong Han -
Patent number: 7763550Abstract: A layer is formed on a semiconductor wafer in an apparatus having a processing chamber, a transferring chamber, and a wafer boat. The boat having the semiconductor wafer thereon is rotated in the transferring chamber. While the boat is rotated, the boat is transferred between the transferring chamber and the processing chamber and a reaction gas is provided to the processing chamber to form the layer on the wafer.Type: GrantFiled: February 18, 2005Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Sang Yahng, Young-Wook Park, Jae-Jong Han, Jum-Soo Chang
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Publication number: 20090108323Abstract: A method of manufacturing a non-volatile memory device is provided. The method includes forming isolation patterns defining an active region on a substrate, forming a floating gate pattern on the active region, and forming a gate line on the floating gate pattern. The floating gate pattern is self-aligned on the active region and has an impurity ion concentration that becomes relatively low as the floating gate pattern gets nearer to the active region.Type: ApplicationFiled: August 15, 2008Publication date: April 30, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Jung-Geun Jee, Ho-Min Son, Yong-Woo Hyung, Jae-Jong Han, Taek-Jin Lim