Patents by Inventor Jae Jung Kim

Jae Jung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12217561
    Abstract: The present invention relates to a dock shelter module that is disposed at a side of a warehouse and connects the inside and outside of the warehouse, dock shelter module comprising: a top frame; a pair of side frames coupled to both sides of the top frame, longitudinally extending, and forming a loading-unloading space in cooperation with the top frame; a bottom frame coupled to the lower ends of the side frames and having a dock leveler seated thereon; a first gate coupled to the top frame, disposed at the front of the loading-unloading space, and opening and closing the outside of the warehouse and the loading-unloading space; a second gate coupled to the top frame, disposed at the rear of the loading-unloading space, and opening and closing the inside of the warehouse and the loading-unloading space; and an air curtain generator installed on the bottom of the top frame between the first gate and the second gate, and forming an air curtain in the loading-unloading space in accordance with whether the first
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 4, 2025
    Inventor: Jae Jung Kim
  • Patent number: 12062706
    Abstract: A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: August 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Sang Yong Kim, Byoung Hoon Lee, Chan Hyeong Lee
  • Patent number: 11967595
    Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 23, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
  • Patent number: 11784260
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: October 10, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
  • Publication number: 20220352389
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Application
    Filed: July 12, 2022
    Publication date: November 3, 2022
    Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
  • Publication number: 20220254884
    Abstract: A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.
    Type: Application
    Filed: October 18, 2021
    Publication date: August 11, 2022
    Inventors: Jae-Jung KIM, Sang Yong KIM, Byoung Hoon LEE, Chan Hyeong LEE
  • Patent number: 11411124
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 9, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
  • Publication number: 20220237968
    Abstract: The present invention relates to a dock shelter module that is disposed at a side of a warehouse and connects the inside and outside of the warehouse, dock shelter module comprising: a top frame; a pair of side frames coupled to both sides of the top frame, longitudinally extending, and forming a loading-unloading space in cooperation with the top frame; a bottom frame coupled to the lower ends of the side frames and having a dock leveler seated thereon; a first gate coupled to the top frame, disposed at the front of the loading-unloading space, and opening and closing the outside of the warehouse and the loading-unloading space; a second gate coupled to the top frame, disposed at the rear of the loading-unloading space, and opening and closing the inside of the warehouse and the loading-unloading space; and an air curtain generator installed on the bottom of the top frame between the first gate and the second gate, and forming an air curtain in the loading-unloading space in accordance with whether the first
    Type: Application
    Filed: June 12, 2020
    Publication date: July 28, 2022
    Inventor: Jae Jung KIM
  • Patent number: 11127739
    Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
  • Publication number: 20210151610
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
  • Patent number: 10923602
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jung Kim, Dong-Soo Lee, Sang-Yong Kim, Jin-Kyu Jang, Won-Keun Chung, Sang-Jin Hyun
  • Publication number: 20210013207
    Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Inventors: Jae Jung KIM, Young Suk CHAI, Sang Yong KIM, Hoon Joo NA, Sang Jin HYUN
  • Patent number: 10892342
    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 12, 2021
    Inventors: Wonkeun Chung, Jae-Jung Kim, Jinkyu Jang, Sangyong Kim, Hoonjoo Na, Dongsoo Lee, Sangjin Hyun
  • Publication number: 20200381311
    Abstract: A semiconductor device may include a channel pattern stacked on a substrate and a gate electrode on the substrate. The channel pattern includes semiconductor patterns. The gate electrode extends to cross the channel pattern. The gate electrode may include dielectric layers, first work function adjusting patterns, and second work function adjusting patterns. The dielectric layers may enclose the semiconductor patterns, respectively. The first work function adjusting patterns may enclose the dielectric layers, respectively, and the second work function adjusting patterns may enclose the first work function adjusting patterns, respectively. The first work function adjusting patterns may be formed of an aluminum-containing material, and each corresponding one of the first work function adjusting patterns may be in contact with a corresponding one of the second work function adjusting patterns enclosing the corresponding one of the first work function adjusting patterns.
    Type: Application
    Filed: December 9, 2019
    Publication date: December 3, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jung Kim, Chanhyeong Lee, Jinkyu Jang, Rakhwan Kim, Dongsoo Lee
  • Patent number: 10847515
    Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 24, 2020
    Inventors: Jae Jung Kim, Young Suk Chai, Sang Yong Kim, Hoon Joo Na, Sang Jin Hyun
  • Publication number: 20200194565
    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Inventors: Wonkeun Chung, Jae-Jung Kim, Jinkyu Jang, Sangyong Kim, Hoonjoo Na, Dongsoo Lee, Sangjin Hyun
  • Patent number: 10619762
    Abstract: The present invention provides an apparatus and a method for detecting a piping alignment using image information and laser sensors capable of precisely and accurately measuring and aligning the alignment of the entire pipes. The apparatus includes: a fixed plate installed on a base stage and having a reference pipe located thereon; a movable plate installed on the base stage along three axes to face the reference pipe and has an aligning pipe located thereon; a circular stage installed between the reference and aligning pipes and is configured to rotate and move along three axes so as to detect levelness and deformations of the reference and aligning pipes; a laser sensor and an imaging device installed on an upper side of the circular stage; and a controller configured to control the laser sensor and the imaging device and determine an alignment of the aligning pipe.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 14, 2020
    Assignee: Mokpo National Maritime University Industry-Academic Cooperation Foundation
    Inventors: Taek-kun Nam, Jin-man Kim, Heon-hui Kim, Jae-jung Kim
  • Patent number: 10615264
    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 7, 2020
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Wonkeun Chung, Jae-Jung Kim, Jinkyu Jang, Sangyong Kim, Hoonjoo Na, Dongsoo Lee, Sangjin Hyun
  • Publication number: 20200035842
    Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.
    Type: Application
    Filed: August 6, 2019
    Publication date: January 30, 2020
    Inventors: Jae-Jung KIM, Dong-Soo LEE, Sang-Yong KIM, Jin-Kyu JANG, Won-Keun CHUNG, Sang-Jin HYUN
  • Publication number: 20200035801
    Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Wonkeun Chung, Jae-Jung Kim, Jinkyu Jang, Sangyong Kim, Hoonjoo Na, Dongsoo Lee, Sangjin Hyun