Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Abstract: The present invention provides an apparatus and a method for detecting a piping alignment using image information and laser sensors capable of precisely and accurately measuring and aligning the alignment of the entire pipes. The apparatus includes: a fixed plate installed on a base stage and having a reference pipe located thereon; a movable plate installed on the base stage along three axes to face the reference pipe and has an aligning pipe located thereon; a circular stage installed between the reference and aligning pipes and is configured to rotate and move along three axes so as to detect levelness and deformations of the reference and aligning pipes; a laser sensor and an imaging device installed on an upper side of the circular stage; and a controller configured to control the laser sensor and the imaging device and determine an alignment of the aligning pipe.

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Abstract: The present invention provides an apparatus and a method for detecting a piping alignment using image information and laser sensors capable of precisely and accurately measuring and aligning the alignment of the entire pipes. The apparatus includes: a fixed plate installed on a base stage and having a reference pipe located thereon; a movable plate installed on the base stage along three axes to face the reference pipe and has an aligning pipe located thereon; a circular stage installed between the reference and aligning pipes and is configured to rotate and move along three axes so as to detect levelness and deformations of the reference and aligning pipes; a laser sensor and an imaging device installed on an upper side of the circular stage; and a controller configured to control the laser sensor and the imaging device and determine an alignment of the aligning pipe.

Abstract: The present invention provides an apparatus and a method for detecting a piping alignment using image information and laser sensors capable of precisely and accurately measuring and aligning the alignment of the entire pipes. The apparatus includes: a fixed plate installed on a base stage and having a reference pipe located thereon; a movable plate installed on the base stage along three axes to face the reference pipe and has an aligning pipe located thereon; a circular stage installed between the reference and aligning pipes and is configured to rotate and move along three axes so as to detect levelness and deformations of the reference and aligning pipes; a laser sensor and an imaging device installed on an upper side of the circular stage; and a controller configured to control the laser sensor and the imaging device and determine an alignment of the aligning pipe.

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

Abstract: Apparatuses and methods for cell and tissue assays and agent delivery are generally described.

Abstract: An ultra-low silicon wire for welding having excellent porosity resistance and electrodeposition coating properties is provided. The ultra-low silicon wire for welding having excellent porosity resistance and electrodeposition coating properties includes: by wt %, 0.001 to 0.30% of C; 0.15% or less of Si; 0.50 to 3.00% of Mn; 0.030% or less of P; 0.030% or less of S; and a balance of Fe and inevitable impurities.

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Abstract: The present invention provides an apparatus and a method for detecting a piping alignment using image information and laser sensors capable of precisely and accurately measuring and aligning the alignment of the entire pipes. The apparatus includes: a fixed plate installed on a base stage and having a reference pipe located thereon; a movable plate installed on the base stage along three axes to face the reference pipe and has an aligning pipe located thereon; a circular stage installed between the reference and aligning pipes and is configured to rotate and move along three axes so as to detect levelness and deformations of the reference and aligning pipes; a laser sensor and an imaging device installed on an upper side of the circular stage; and a controller configured to control the laser sensor and the imaging device and determine an alignment of the aligning pipe.

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

Abstract: Embodiments of the disclosure include methods and apparatus for electrically grounding a shadow mask for use in a deposition chamber. In one embodiment, a substrate support is provided and includes a substrate receiving surface, and a plurality of compressible grounding devices disposed about a periphery of the substrate receiving surface. Each of the plurality of grounding devices comprises a base member fixed to the substrate support, and a biasing assembly movably disposed in the base member.

Abstract: Provided is a method of fabricating a semiconductor device, including forming an interlayered insulating layer having an opening, on a substrate; sequentially forming a first conductive pattern, a barrier pattern, and a second conductive pattern on bottom and side surfaces of the opening; and nitrifying an upper portion of the second conductive pattern to form a metal nitride layer that is spaced apart from the first conductive pattern.