Abstract: A coupling compensator for a display panel and a display device including the coupling compensator are disclosed. In one aspect, the coupling compensator includes a memory configured to receive grayscale data and store the grayscale data and a first data converter configured to convert the grayscale data to a plurality of grayscale data voltages including first and second grayscale data voltages. The compensator also includes a coupling voltage calculator configured to calculate a line coupling voltage generated on a data line based on the difference between the first grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an (N?1)th row and the second grayscale data voltage corresponding to the grayscale data provided to a first group of the pixels in an Nth row, where the N is an integer equal to or greater than 2.

Abstract: A display device includes: a display unit including a plurality of pixels, each of the pixels including: an OLED; and a driving transistor to supply current to an anode of the OLED according to a voltage applied to a gate of the driving transistor and a power supply voltage; a scan driver to supply scan signals to the pixels; an initialization driver to supply initializing signals to the pixels; a data driver to supply data signals to the pixels; light emission drivers to supply first and second light emission signals to the pixels; and a power supply to supply the power supply voltage and an initialization voltage to the pixels, wherein the initialization voltage is supplied to the anode during a first period, and the power supply voltage corresponding to a threshold voltage of the driving transistor is supplied to the gate during a first sub-period of the first period.

Abstract: In a touch substrate and a display apparatus, the touch substrate includes a first electrode, a second electrode, a first touch electrode and a blocking layer. The first electrode includes an opaque conductive material and extends along a first direction. The second electrode includes the opaque conductive material, extends along a second direction crossing the first direction, and has a gap through which the first electrode extends. The first touch electrode is formed on the first electrode and is electrically connected to the first electrode. The blocking layer overlaps the first and second electrodes.

Abstract: A pixel, a display device having the same, and a thin film transistor (TFT) substrate for the display device are disclosed. In one aspect, the pixel includes an emitter configured to emit light based at least in part on a driving current. The pixel also includes a driving transistor including an active layer, a first electrode electrically connected to a first end portion of the active layer, a second electrode electrically connected to a second end portion of the active layer, a first gate electrode configured to receive a data voltage from a data driver so as to form a channel in the active layer, and a second gate electrode configured to receive a bias voltage from a voltage source, wherein the channel is configured to adjust the driving current.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract: A pixel circuit and an OLED display including the same are disclosed. The pixel circuit includes a driving transistor having a double gate structure, the driving transistor including a first gate electrode electrically connected to a first node, a second gate electrode electrically connected to a second node, a first electrode electrically connected to a first power supply voltage, and a second electrode electrically connected to the anode of the OLED. The pixel circuit also includes a switching transistor including a gate electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode electrically connected to the first node. The pixel circuit further includes a storage capacitor and a compensation capacitor including a first electrode electrically connected to the second node and a second electrode electrically connected to the first electrode of the driving transistor.

Abstract: A gate driver includes a stage including an input unit including a first transistor diode-connected to a first input terminal of the stage through a first node and biased by a first input signal of the first input terminal, an output unit including a second transistor including a gate electrode coupled to the first node, a first electrode coupled to a clock input terminal, and a second electrode coupled to a first output terminal of the stage, a capacitor coupled between the gate electrode and the second electrode of the second transistor, and a noise remover including a third transistor including a gate electrode coupled to a second node, a first electrode coupled to the first node, and a second electrode coupled to a first voltage input terminal of the stage which receives a first voltage.

Abstract: A gate driving circuit including a plurality of gate driving units respectively coupled to a plurality of gate lines, each of the plurality of gate driving units includes a carry unit configured to output a carry signal, a pull-up unit configured to output a gate signal, and a pull-down unit configured to pull down an output node of the gate signal.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A display substrate includes a base substrate including a display area in which signal lines and pixels are arranged and a peripheral area surrounding the display area, pads disposed in the peripheral area and receiving an electrical signal, fan-out lines connecting the pads and the signal lines, and static electricity breakup circuits comprising a breakup line that crosses the fan-out lines, and static electricity prevention circuits respectively connected to the fan-out lines. Parts of the static electricity prevention circuits are connected to adjacent fan-out lines and are commonly connected to the one of the breakup lines through a common contact part.

Abstract: A gate driver and a display device are disclosed. In one aspect, the gate driver includes a plurality of stages connected in cascade. Each of the stages includes an input unit, an output unit and a carry signal generator. The input unit connects a first input terminal and a first node and includes a first input transistor and a second input transistor. The output unit connects the first node and a first output terminal and includes an output transistor and an output capacitor. The carry signal generator connects a clock terminal and a second output terminal. An output terminal of the first input transistor and an input terminal of the second input terminal are connected to a second node. The input unit further includes a diode-connected transistor applying a carry signal from the first output terminal to the second node.

Abstract: A gate driver includes a plurality of stages connected to each other in a cascade manner, where each of the stages includes an input unit which connects a first input terminal and a first node and includes a first input transistor and a second input transistor, where an output terminal of the first input transistor and an input terminal of the second input transistor are connected to a second node, and the input unit further includes a storage capacitor which connects the first input terminal and the second node.

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract: A display device includes a display area including a gate line and a data line and a gate driver connected to an end of the gate line, the gate driver including at least one stages integrated on a substrate configured to output a gate voltage, in which the stage includes an inverter unit and an output unit, in which the output unit includes a first transistor and a first capacitor. The first transistor includes an input terminal applied with a clock signal, a control terminal connected to the node Q, and an output terminal connected to a gate voltage output terminal through which the gate voltage is output. An inverter voltage output from the inverter is lower than the low voltage of the gate voltage output by the output unit.

Abstract: A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.