Abstract: Provided herein may be a semiconductor memory device, a controller, and a memory system having the same. By means of a method of operating the controller of the memory system, the semiconductor memory device, which is included in the memory system and including a plurality of memory blocks, is controlled. The method of operating the controller may include sensing a power-on state of the memory system, and performing an erased block scan operation on the plurality of memory blocks using a scan read voltage, based on sensing that the memory system is in the power-on state. Each of memory cells in the plurality of memory blocks may store at least two bits of data, and the scan read voltage may enable an erase state and a program state of the memory cells to be distinguished from each other.

Abstract: Disclosed are: a thermoplastic elastomer resin composition comprising a thermoplastic elastomer resin and, as a reactive additive, a compound containing one or more isocyanurate functional groups; a molded product comprising the same.

Abstract: Provided herein may be a semiconductor memory device, a controller, and a memory system having the same. By means of a method of operating the controller of the memory system, the semiconductor memory device, which is included in the memory system and including a plurality of memory blocks, is controlled. The method of operating the controller may include sensing a power-on state of the memory system, and performing an erased block scan operation on the plurality of memory blocks using a scan read voltage, based on sensing that the memory system is in the power-on state. Each of memory cells in the plurality of memory blocks may store at least two bits of data, and the scan read voltage may enable an erase state and a program state of the memory cells to be distinguished from each other.

Abstract: The present invention relates to a thermoplastic polyether ester elastomer (TPEE) having a hard segment and a soft segment and a method for preparing the same and, more specifically, to a thermoplastic polyether ester elastomer and a method for preparing the same, wherein a unit derived from an anhydrosugar alcohol derivative with improved reactivity derived from biomass is contained in the soft segment, and thus through the adjustment of the content of the anhydrosugar alcohol derivative, elastic characteristics and physical characteristics (for example, hardness, etc.), which are important characteristics of an elastomer, can be favorably maintained, the melting point variously required in the molding process of a final product can be easily controlled, a problem of depletion of, especially, petroleum resources as finite resources, can be solved, and environmental friendliness can be improved.

Abstract: Disclosed are: a thermoplastic elastomer resin composition comprising a thermoplastic elastomer resin and, as a reactive additive, a compound containing one or more isocyanurate functional groups; a molded product comprising the same.

Abstract: The present invention relates to a thermoplastic polyether ester elastomer (TPEE) having a hard segment and a soft segment and a method for preparing the same and, more specifically, to a thermoplastic polyether ester elastomer and a method for preparing the same, wherein a unit derived from an anhydrosugar alcohol derivative with improved reactivity derived from biomass is contained in the soft segment, and thus through the adjustment of the content of the anhydrosugar alcohol derivative, elastic characteristics and physical characteristics (for example, hardness, etc.), which are important characteristics of an elastomer, can be favorably maintained, the melting point variously required in the molding process of a final product can be easily controlled, a problem of depletion of, especially, petroleum resources as finite resources, can be solved, and environmental friendliness can be improved.

Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

Abstract: An integrated circuit includes a node setting block connected to a reference node and suitable for setting a voltage level of the reference node to a reference voltage level, a plurality of control voltage generation units connected in series to a reference node and suitable for generating a plurality of control voltages of which voltage level is variable and a current sensing circuit suitable for sensing a variation of a current flowing through a signal transmission line by using the plurality of control voltages, the signal transmission line connected to an internal circuit and a voltage level of the signal transmission line being fixed.

Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.

Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

Abstract: An integrated circuit includes a node setting block connected to a reference node and suitable for setting a voltage level of the reference node to a reference voltage level, a plurality of control voltage generation units connected in series to a reference node and suitable for generating a plurality of control voltages of which voltage level is variable and a current sensing circuit suitable for sensing a variation of a current flowing through a signal transmission line by using the plurality of control voltages, the signal transmission line connected to an internal circuit and a voltage level of the signal transmission line being fixed.

Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.

Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.

Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.

Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

Abstract: A voltage supply circuit includes a pump voltage generator for generating an input voltage by changing a power source voltage to a desired level and changing a level of the input voltage according to a rising time of an operating voltage.

Abstract: A voltage supply circuit includes a pump voltage generator for generating an input voltage by changing a power source voltage to a desired level and changing a level of the input voltage according to a rising time of an operating voltage.

Abstract: A buffer circuit of a semiconductor integrated apparatus includes a control block configured to output a result of comparing an input voltage level and an output voltage level as a control signal, and a buffering block configured to generate an output voltage having the substantially same level as an input voltage in response to the control signal.

Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

Abstract: A semiconductor memory device includes cells strings including memory cells and coupled between a common source line and bit lines, respectively, a peripheral circuit configured to store data in the memory cells or read data stored in the memory cells, a main voltage supply unit configured to generate operating voltages to be supplied to the peripheral circuit, a precharge voltage supply unit configured to generate a precharge voltage for precharging the bit lines, and a switching circuit configured to transfer the precharge voltage to the common source line and one of the bit lines when a bit line precharge operation is performed.