Patents by Inventor Jae Kwan Kwon

Jae Kwan Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11550492
    Abstract: Provided herein may be a semiconductor memory device, a controller, and a memory system having the same. By means of a method of operating the controller of the memory system, the semiconductor memory device, which is included in the memory system and including a plurality of memory blocks, is controlled. The method of operating the controller may include sensing a power-on state of the memory system, and performing an erased block scan operation on the plurality of memory blocks using a scan read voltage, based on sensing that the memory system is in the power-on state. Each of memory cells in the plurality of memory blocks may store at least two bits of data, and the scan read voltage may enable an erase state and a program state of the memory cells to be distinguished from each other.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: January 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Jae Kwan Kwon
  • Patent number: 11453775
    Abstract: Disclosed are: a thermoplastic elastomer resin composition comprising a thermoplastic elastomer resin and, as a reactive additive, a compound containing one or more isocyanurate functional groups; a molded product comprising the same.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 27, 2022
    Assignee: SAMYANG CORPORATION
    Inventors: Jae-Kwan Kwon, Jin Yoo, Cheol-Han Lee, Yong-Chan Lim, Sang-Hyun Park
  • Publication number: 20220083253
    Abstract: Provided herein may be a semiconductor memory device, a controller, and a memory system having the same. By means of a method of operating the controller of the memory system, the semiconductor memory device, which is included in the memory system and including a plurality of memory blocks, is controlled. The method of operating the controller may include sensing a power-on state of the memory system, and performing an erased block scan operation on the plurality of memory blocks using a scan read voltage, based on sensing that the memory system is in the power-on state. Each of memory cells in the plurality of memory blocks may store at least two bits of data, and the scan read voltage may enable an erase state and a program state of the memory cells to be distinguished from each other.
    Type: Application
    Filed: March 17, 2021
    Publication date: March 17, 2022
    Inventor: Jae Kwan KWON
  • Patent number: 10995212
    Abstract: The present invention relates to a thermoplastic polyether ester elastomer (TPEE) having a hard segment and a soft segment and a method for preparing the same and, more specifically, to a thermoplastic polyether ester elastomer and a method for preparing the same, wherein a unit derived from an anhydrosugar alcohol derivative with improved reactivity derived from biomass is contained in the soft segment, and thus through the adjustment of the content of the anhydrosugar alcohol derivative, elastic characteristics and physical characteristics (for example, hardness, etc.), which are important characteristics of an elastomer, can be favorably maintained, the melting point variously required in the molding process of a final product can be easily controlled, a problem of depletion of, especially, petroleum resources as finite resources, can be solved, and environmental friendliness can be improved.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: May 4, 2021
    Assignee: SAMYANG CORPORATION
    Inventors: Min Sun Lee, Mi Ran Kim, Yun Ju Chang, Jae Kwan Kwon, Cheol Han Lee, Young Do Kwon
  • Publication number: 20210061991
    Abstract: Disclosed are: a thermoplastic elastomer resin composition comprising a thermoplastic elastomer resin and, as a reactive additive, a compound containing one or more isocyanurate functional groups; a molded product comprising the same.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 4, 2021
    Applicant: SAMYANG CORPORATION
    Inventors: Jae-Kwan KWON, Jin YOO, Cheol-Han LEE, Yong-Chan LIM, Sang-Hyun PARK
  • Publication number: 20200071518
    Abstract: The present invention relates to a thermoplastic polyether ester elastomer (TPEE) having a hard segment and a soft segment and a method for preparing the same and, more specifically, to a thermoplastic polyether ester elastomer and a method for preparing the same, wherein a unit derived from an anhydrosugar alcohol derivative with improved reactivity derived from biomass is contained in the soft segment, and thus through the adjustment of the content of the anhydrosugar alcohol derivative, elastic characteristics and physical characteristics (for example, hardness, etc.), which are important characteristics of an elastomer, can be favorably maintained, the melting point variously required in the molding process of a final product can be easily controlled, a problem of depletion of, especially, petroleum resources as finite resources, can be solved, and environmental friendliness can be improved.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 5, 2020
    Applicant: SAMYANG CORPORATION
    Inventors: Min Sun LEE, Mi Ran KIM, Yun Ju CHANG, Jae Kwan KWON, Cheol Han LEE, Young Do KWON
  • Patent number: 9419007
    Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jae Kwan Kwon
  • Patent number: 9360877
    Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jae-Kwan Kwon
  • Patent number: 9360880
    Abstract: An integrated circuit includes a node setting block connected to a reference node and suitable for setting a voltage level of the reference node to a reference voltage level, a plurality of control voltage generation units connected in series to a reference node and suitable for generating a plurality of control voltages of which voltage level is variable and a current sensing circuit suitable for sensing a variation of a current flowing through a signal transmission line by using the plurality of control voltages, the signal transmission line connected to an internal circuit and a voltage level of the signal transmission line being fixed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jae-Kwan Kwon
  • Publication number: 20160020217
    Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.
    Type: Application
    Filed: December 15, 2014
    Publication date: January 21, 2016
    Inventor: Jae Kwan KWON
  • Publication number: 20140354260
    Abstract: An integrated circuit includes a node setting block connected to a reference node and suitable for setting a voltage level of the reference node to a reference voltage level, a plurality of control voltage generation units connected in series to a reference node and suitable for generating a plurality of control voltages of which voltage level is variable and a current sensing circuit suitable for sensing a variation of a current flowing through a signal transmission line by using the plurality of control voltages, the signal transmission line connected to an internal circuit and a voltage level of the signal transmission line being fixed.
    Type: Application
    Filed: December 16, 2013
    Publication date: December 4, 2014
    Applicant: SK hynix Inc.
    Inventor: Jae-Kwan KWON
  • Publication number: 20140320097
    Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventor: Jae-Kwan KWON
  • Patent number: 8810306
    Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 19, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae-Kwan Kwon
  • Publication number: 20140167839
    Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 19, 2014
    Applicant: SK HYNIX INC.
    Inventor: Jae-Kwan KWON
  • Patent number: 8441867
    Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: May 14, 2013
    Assignee: SK hynix Inc.
    Inventor: Jae-Kwan Kwon
  • Patent number: 8421523
    Abstract: A voltage supply circuit includes a pump voltage generator for generating an input voltage by changing a power source voltage to a desired level and changing a level of the input voltage according to a rising time of an operating voltage.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: April 16, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jae Kwan Kwon
  • Publication number: 20120139621
    Abstract: A voltage supply circuit includes a pump voltage generator for generating an input voltage by changing a power source voltage to a desired level and changing a level of the input voltage according to a rising time of an operating voltage.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 7, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jae Kwan KWON
  • Patent number: 8130012
    Abstract: A buffer circuit of a semiconductor integrated apparatus includes a control block configured to output a result of comparing an input voltage level and an output voltage level as a control signal, and a buffering block configured to generate an output voltage having the substantially same level as an input voltage in response to the control signal.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Kwan Kwon, Sung-Joo Ha
  • Publication number: 20120032724
    Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.
    Type: Application
    Filed: October 10, 2011
    Publication date: February 9, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Jae Kwan Kwon
  • Publication number: 20120008419
    Abstract: A semiconductor memory device includes cells strings including memory cells and coupled between a common source line and bit lines, respectively, a peripheral circuit configured to store data in the memory cells or read data stored in the memory cells, a main voltage supply unit configured to generate operating voltages to be supplied to the peripheral circuit, a precharge voltage supply unit configured to generate a precharge voltage for precharging the bit lines, and a switching circuit configured to transfer the precharge voltage to the common source line and one of the bit lines when a bit line precharge operation is performed.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 12, 2012
    Inventors: Joo Yun HA, Jae Kwan KWON