Abstract: A semiconductor memory device includes cells strings including memory cells and coupled between a common source line and bit lines, respectively, a peripheral circuit configured to store data in the memory cells or read data stored in the memory cells, a main voltage supply unit configured to generate operating voltages to be supplied to the peripheral circuit, a precharge voltage supply unit configured to generate a precharge voltage for precharging the bit lines, and a switching circuit configured to transfer the precharge voltage to the common source line and one of the bit lines when a bit line precharge operation is performed.

Abstract: A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

Abstract: A power-on reset signal generation circuit of a semiconductor memory apparatus includes an external voltage level detector configured to detect an external voltage and generate an external voltage detection signal; a band gap voltage generation unit configured to generate a band gap voltage in response to the external voltage detection signal; a level detection voltage dividing unit configured to divide the external voltage depending upon a level of the band gap voltage and generate a division voltage; and a power-on reset signal generation unit configured to compare the level of the band gap voltage with a level of the division voltage and generate a power-on reset signal.

Abstract: A pumping voltage generating circuit in a semiconductor memory apparatus includes a voltage supplying unit configured to supply an external power supply voltage to a first node in response to a first transfer signal, a node control unit configured to couple the first node to a second node in response to a second transfer signal and to couple the second node to an output node in response to a third transfer signal, a first pumping unit configured to increase a voltage level on the first node through a pumping operation that is performed in response to a first oscillation signal and to control one of an amount of voltage increment and decrement on the first node in response to a first control signal, and a second pumping unit configured to increase a voltage level on the second node through a pumping operation that is performed in response to a second oscillation signal and to control one of an amount of voltage increment and decrement on the second node in response to a second control signal.

Abstract: A pumping voltage generating circuit in a semiconductor memory apparatus includes a voltage supplying unit configured to supply an external power supply voltage to a first node in response to a first transfer signal, a node control unit configured to couple the first node to a second node in response to a second transfer signal and to couple the second node to an output node in response to a third transfer signal, a first pumping unit configured to increase a voltage level on the first node through a pumping operation that is performed in response to a first oscillation signal and to control one of an amount of voltage increment and decrement on the first node in response to a first control signal, and a second pumping unit configured to increase a voltage level on the second node through a pumping operation that is performed in response to a second oscillation signal and to control one of an amount of voltage increment and decrement on the second node in response to a second control signal.

Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

Abstract: A buffer circuit of a semiconductor integrated apparatus includes a control block configured to output a result of comparing an input voltage level and an output voltage level as a control signal, and a buffering block configured to generate an output voltage having the substantially same level as an input voltage in response to the control signal.

Abstract: An internal voltage generation circuit of semiconductor memory device includes a reference voltage generation unit configured to generate a reference voltage, and a pumping control unit configured to be enabled at every active mode, compare the reference voltage with a fed-back voltage of a pumping voltage terminal, and output a pumping enable signal based on a comparison result. A storage unit is configured to store and output the pumping enable signal outputted from the pumping control unit. A charge pumping unit is configured to drive the pumping voltage terminal by performing a charge pumping operation in response to the pumping enable signal outputted from the storage unit.

Abstract: An internal voltage generator of a semiconductor memory device generates pumping voltages (VPP, VBB, etc.) as internal voltages, which is capable of improving a charge pumping scheme. The internal voltage generator includes a plurality of charge pumping units for generating a pumping voltage by performing a charge pumping operation according to a plurality of pumping enable signals, and a pumping controller for controlling a number of the pumping enable signals to be activated according to a level of a fed-back pumping voltage.