Abstract: Disclosed is a method of manufacturing a polyurethane filter foam having excellent air permeability, elasticity, and restoring force. In the method of manufacturing the polyurethane filter foam, the cell size of the filter foam is made regular by controlling the pressure by adjusting the diameter of the foaming head of a foaming machine, rather than adding a cell opener, cell irregularity caused by poor dispersion of the cell opener is alleviated, and air permeability, porosity, and compression set are excellent.

Abstract: The present invention relates to a multi-component host material and an organic electroluminescent device comprising the same. By comprising a specific combination of the multi-component host compounds, the organic electroluminescent device according to the present invention can provide high luminous efficiency and excellent lifespan characteristics.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: A polishing composition includes abrasive particles, a pyrrolidone containing a hydrophilic group, a dispersing agent, a first dishing inhibitor including polyacrylic acid, and a second dishing inhibitor including a non-ionic polymer.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A polishing composition includes abrasive particles, a pyrrolidone containing a hydrophilic group, a dispersing agent, a first dishing inhibitor including polyacrylic acid, and a second dishing inhibitor including a non-ionic polymer.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Provided is a chemical mechanical polishing (CMP) apparatus that includes a swing unit installed apart from a platen, on which a CMP pad to be conditioned is placed, at a predetermined interval, a connector installed on an upper end of the swing unit at one end thereof in a perpendicular direction to the swing unit and pivoting around the swing unit above the CMP pad, a rotator rotatably installed on the other end of the connector, a CMP pad conditioner coupled to the rotator and conditioning the CMP pad when rotated, and a vibration meter installed on the connector and detecting vibrations to measure a vibration acceleration of the CMP pad conditioner, thereby predicting a wear rate of the CMP pad based on the vibration acceleration and a state in which the CMP pad conditioner is installed or being used.

Abstract: This invention relates to a conditioner for a CMP (Chemical Mechanical Polishing) pad, which is used in a CMP process which is part of the fabrication of a semiconductor device, and more particularly, to a CMP pad conditioner in which the structure of the cutting tips is such that the change in the wear of the polishing pad is not great even when different kinds of slurry are used and when there are changes in pressure of the conditioner, and to a method of manufacturing the same.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: Provided is a chemical mechanical polishing (CMP) apparatus that includes a swing unit installed apart from a platen, on which a CMP pad to be conditioned is placed, at a predetermined interval, a connector installed on an upper end of the swing unit at one end thereof in a perpendicular direction to the swing unit and pivoting around the swing unit above the CMP pad, a rotator rotatably installed on the other end of the connector, a CMP pad conditioner coupled to the rotator and conditioning the CMP pad when rotated, and a vibration meter installed on the connector and detecting vibrations to measure a vibration acceleration of the CMP pad conditioner, thereby predicting a wear rate of the CMP pad based on the vibration acceleration and a state in which the CMP pad conditioner is installed or being used.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: A method of manufacturing a semiconductor devices includes providing a semiconductor substrate that includes a channel region. The method includes forming a gate electrode material film including a stepped portion on the channel region. A sacrificial material film that has an etch selectivity that is the same as an etch selectivity of the gate electrode material film is formed. The sacrificial material film is planarized until a top surface of the gate electrode material film is exposed. The stepped portion is reduced by removing an exposed portion of the gate electrode material film.

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Abstract: This invention relates to a conditioner for a CMP (Chemical Mechanical Polishing) pad, which is used in a CMP process which is part of the fabrication of a semiconductor device, and more particularly, to a CMP pad conditioner in which the structure of the cutting tips is such that the change in the wear of the polishing pad is not great even when different kinds of slurry are used and when there are changes in pressure of the conditioner, and to a method of manufacturing the same.

Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.