Abstract: A polishing pad may include a base and a plurality of polishing protrusions on a surface of the base. Each polishing protrusion may include a sidewall defining an opening in a surface of the polishing protrusion opposite the base. In addition, portions of the sidewall opposite the base may define a contact surface.

Abstract: A pad conditioning disk, a pre-conditioning unit, and a CMP apparatus having the same are provided. The pad conditioning disk includes a base in which mountain-type tips and valley-type grooves are repeatedly connected to each other, and a cutting layer formed on the base layer. The cutting layer including conditioning particles deposited on surfaces of the tips and grooves. A surfaces roughness of conditioning particles deposited on the surfaces of the tips is less than a surface roughness of conditioning particles deposited on the surfaces of the grooves.

Abstract: A polishing pad may include a base and a plurality of polishing protrusions on a surface of the base. Each polishing protrusion may include a sidewall defining an opening in a surface of the polishing protrusion opposite the base. In addition, portions of the sidewall opposite the base may define a contact surface.

Abstract: Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.

Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

Abstract: A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.

Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

Abstract: A multi-level transistor comprising a second active region having a single-crystalline characteristic and a method for manufacturing the multi-level transistor are disclosed. The multi-level transistor comprises a substrate comprising a first active region, a first transistor formed on the first active region, a first insulating layer covering the first transistor, and adapted to isolate the first active region, a second active region comprising a patterned first selective epitaxial growth (SEG) layer formed on the first insulating layer, and a second transistor formed on the second active region.

Abstract: For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.

Abstract: Slurry compositions and method used in a chemical-mechanical polishing process for manufacturing a semiconductor device may include a surfactant and a positive-ionic high molecular compound. The surfactant and the positive-ionic high molecular compound may form first and second passivation layers on the surface of an exposed polysilicon layer.

Abstract: Integrated circuit devices include a semiconductor substrate having a first doped region and a second doped region having a different doping type than the first doped region. A gate electrode structure on the semiconductor substrate extends between the first and second doped regions and has a gate insulation layer of a first high dielectric constant material in the first doped region and of a second high dielectric constant material, different from the first high dielectric constant material, in the second doped region. A gate electrode is on the gate insulation layer.

Abstract: For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.

Abstract: A method for forming a filling film having an even surface and a method for forming a trench isolation using a polishing process. After a substrate having stepped portions thereon is provided, a film is formed on the substrate to cover the stepped portions of the substrate. The edge of the stepped portion of the film is processed to have a round shape, and then the film including the round shaped edge portion is chemical-mechanically polished to form the filling film having an even surface. Before the film is polished, the film to be polished is processed to have the round shape, thereby increasing the polishing rate of the film.