Abstract: A battery cell assembly, including: a cell block including a plurality of battery cells; and a side frame disposed on one side surface of the cell block, wherein the side frame includes a side wall portion and a flange portion disposed on the side wall portion on a side opposite the cell block and configured to be fastened to an external support structure, and wherein the side wall portion includes a hollow space formed throughout an inside thereof.

Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Abstract: A thin film transistor is provided. The thin film transistor comprises a gate electrode, an In—Zn—Sn oxide (IZTO) channel layer that overlaps the top or bottom of the gate electrode and has a spinel single-phase crystalline, a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.

Abstract: An identification key generation circuit using process deviation comprises a first semiconductor element portion and a second semiconductor element portion manufactured on a single semiconductor substrate and have different physical characteristics, an identification key generation portion generating an identification key using at least one of a difference in electrical characteristics of the first semiconductor element portion due to a process deviation occurring in the manufacturing process of the first semiconductor element portion and an identification key derivation portion determining the difference in electrical characteristic as a digital value, wherein the first semiconductor element portion is formed on the semiconductor substrate, and the second semiconductor element portion is formed on the upper portion of the first semiconductor element portion, and wherein the first semiconductor element portion and the second semiconductor element portion are connected to each other through at least one layer

Abstract: A display device is disclosed that includes a base substrate, an organic light emitting element disposed on the base substrate, an insulating layer disposed on the base substrate and containing silicon oxide, and a thin film transistor disposed on the base substrate and electrically connected to the organic light emitting element, wherein the thin film transistor includes a semiconductor pattern disposed on the base substrate and including a channel area in contact with the insulating layer, and a gate electrode overlapping the channel area on a plane, wherein the semiconductor pattern contains indium gallium zinc tin oxide.

Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Abstract: Disclosed are a memory device based on an IGO channel layer and a method of fabricating the same. More particularly, the memory device according to an embodiment includes multilayers including at least one transition metal; and a channel layer formed adjacent to the multilayers and configured to include an indium gallium oxide (IGO) material.

Abstract: Provided are a selection element which does not need an intermediate electrode and thus has improved integration, a phase-change memory device having the selection element, and a phase-change memory implemented so that the phase-change memory device has a highly integrated three-dimensional architecture.

Abstract: Various embodiments relate to an oxide semiconductor having improved resistance through cation/anion substitutional doping, and a manufacturing method therefor, in which: an IGZO channel layer is prepared; carrier diffusion is induced in the IGZO channel layer, by using a group 4 element or a group 7 element, so that carriers remain in the IGZO channel layer; and through carrier diffusion, low resistance contact with the IGZO channel layer can be implemented, with respect to a metal electrode. Various embodiments relate to a thin-film transistor having an ohmic junction structure of an oxide semiconductor, and a manufacturing method therefor.

Abstract: The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Abstract: Various embodiments pertain to a high mobility transistor element resulting from IGTO oxide semiconductor crystallization, and a production method for same, the transistor element comprising a substrate and a crystalline IGTO channel layer disposed on the substrate, and being produced by converting a non-crystalline IGTO channel layer provided on the substrate to a crystalline IGTO channel layer.

Abstract: Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.

Abstract: Embodiments of the present disclosure relate to a thin film transistor array substrate and a display device. Since a wavy structure is formed through heat treatment in a structure in which a first buffer layer made of an organic material, a second buffer layer made of a metal oxide and a third buffer layer made of an inorganic material are stacked, it is possible to provide a display device including an array substrate which has stretchable characteristics through the wavy structure while preventing a crack from occurring in the third buffer layer and preventing characteristics of thin film transistors disposed on the third buffer layer from degrading.

Abstract: Tellurium oxide and a thin film transistor comprising the same as a channel layer are provided. The tellurium oxide is a metal oxide including tellurium, wherein a portion of the tellurium is in a Te0 state having a zero oxidation number, and another portion of the tellurium is in a Te4+ ' state having a tetravalent oxidation number.

Abstract: A method for manufacturing a tellurium-based semiconductor device comprises the steps of: preparing a substrate; depositing, on the substrate, a tellurium-based semiconductor material including tellurium and a tellurium oxide so as to form a tellurium-based semiconductor layer; and forming a passivation layer on the tellurium-based semiconductor layer. According to the manufacturing method, heat treatment at a high temperature or cryogenic conditions are not required, and thus, it is possible to manufacture a semiconductor device through a practical process. In addition, since the crystallinity of the tellurium-based semiconductor layer is improved during the manufacturing process, it is possible to provide a p-type semiconductor device having excellent electrical characteristics such as electric field mobility and a current blink ratio.

Abstract: A thin-film transistor comprises a substrate; an insulating layer formed on the substrate; an active layer formed on the insulating layer; and source and drain electrode layers formed on the active layer so as to be spaced from each other, wherein the active layer comprises: a first oxide semiconductor layer consisting of In, Ga and O; and a second oxide semiconductor layer which is formed on the first oxide semiconductor layer and which consists of Zn and O. The thin-film transistor having metal oxide semiconductor layers of a heterojunction structure has greatly improved electron mobility by comprising, as an active layer, oxide semiconductor layers of a heterojunction structure. In addition, the physical properties of a thin-film transistor to be manufactured can be controlled by adjusting the composition and thickness of oxide semiconductor layers through an atomic layer deposition (ALD) process.

Abstract: A thin-film transistor includes a gate electrode, and an active layer insulated from the gate electrode by a gate insulating layer, and the active layer includes a quasi-superlattice structure with a first oxide semiconductor material and a second oxide semiconductor material having a larger bandgap than the first oxide semiconductor material alternately stacked at least twice. A display apparatus includes a thin-film transistor including an active layer of a quasi-superlattice structure for each pixel.

Abstract: A crystalline IZTO oxide semiconductor and a thin film transistor having the same are provided. The thin film transistor includes a gate electrode, a crystalline In—Zn—Sn oxide (IZTO) channel layer overlapping the upper or lower portions of the gate electrode and having hexagonal crystal grains, and a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.

Abstract: A thin film transistor and a non-volatile memory device are provided. The thin film transistor comprises a gate electrode, and a metal oxide channel layer traversing the upper or lower portions of the gate electrode. The metal oxide channel layer has semiconductor properties while having bixbyite crystals. An insulating layer is disposed between the gate electrode and the metal oxide channel layer. Source and drain electrodes are electrically connected to both ends of the metal oxide channel layer, respectively.

Abstract: Provided are a three-dimensional semiconductor memory device, a method for manufacturing the same, a method for operating the same, and an electronic system including the same. The three-dimensional semiconductor memory device includes a substrate, a stack structure on the substrate, and vertical channel structures, which are provided in channel holes penetrating the stack structure, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, a conductive pad, and a vertical semiconductor pattern, wherein the vertical channel pattern includes a first portion contacting the upper surface of the substrate and a second portion provided between the data storage pattern and the vertical semiconductor pattern, and wherein the vertical semiconductor pattern is spaced apart from the substrate with the first portion of the vertical channel pattern therebetween.