Patents by Inventor Jae Kyu An

Jae Kyu An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9406608
    Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jae Kyu Cho, Shan Gao
  • Patent number: 9400263
    Abstract: Provided herein is a robot for inspecting pipelines as it moves along an outer surface of a pipeline, the robot comprising: a plurality of body parts detachably provided along a longitudinal direction of the pipeline; a connector configured to connect adjacent body parts, and to distance one of the connected body parts away from the pipeline so that the plurality of body parts may cross an obstacle; and a controller configured to control the connector to lift one of the body parts to cross an obstacle, with another body part secured to the pipeline.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: July 26, 2016
    Assignee: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Jae Kyu An, Sang Chul Han, Hyungpil Moon
  • Publication number: 20160195769
    Abstract: A backlight unit may include a wall and a plurality of light sources. The wall may have a side in a cross-sectional view of the backlight unit. The side may have a curved shape in the cross-sectional view of the backlight unit. The plurality light sources may include a first light source and a second light source. The second light source may be positioned farther away from a center portion of the wall than the first light source in the cross-sectional view of the backlight unit. A minimum distance between the second light source and the side may be greater than a minimum distance between the first light source and the side in the cross-sectional view of the backlight unit.
    Type: Application
    Filed: April 28, 2015
    Publication date: July 7, 2016
    Inventors: Seung Wan KIM, Young Sup KWON, Jae Kyu PARK, Eun Chul SHIN
  • Patent number: 9378815
    Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells therein, which operate in response to word line driving and column selecting signals. Each of memory cells includes a resistive device and a cell transistor connected in series. An I/O sense amplifier senses and amplifies data output from the memory cell array to thereby generate output data, and also generate program current based on input data and provide the program current to the memory cell array. The resistive memory device is also configured to read output data from the I/O sense amplifier and adjust interface states of the cell transistors based on a voltage level of the output data during a test mode.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Kyu Lee, Dae-Won Kim
  • Patent number: 9368361
    Abstract: In one embodiment, a method for forming an electronic device includes providing a substrate having a plurality of electronic devices formed therein, forming a protective layer over a major surface of the substrate containing the plurality of electronic devices, forming a mold layer over the protective layer, thinning a major surface of the substrate opposite to the major surface containing the plurality of electronic devices, and removing the adhesive layer and the mold layer. In another embodiment, a zone coating layer can be included between the protective layer and the mold layer.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: June 14, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Seung Chul Han, Jae Kyu Song, Do Hyung Kim
  • Publication number: 20160163543
    Abstract: A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 9, 2016
    Inventors: Dae-Won KIM, Jae-Kyu LEE
  • Publication number: 20160163858
    Abstract: A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 9, 2016
    Inventors: Dae-Won KIM, Jae-Kyu LEE
  • Patent number: 9361529
    Abstract: A parking area detecting method includes generating a top view image by capturing images of surroundings of a vehicle, detecting a first directional parking line from the top view image, detecting a second directional parking line having a direction different from a direction of the first directional parking line from the top view image, and detecting a parking area by combining the first directional parking line and the second directional parking line.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: June 7, 2016
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Seong Sook Ryu, Eu Gene Chang, Jae Seob Choi, Dae Joong Yoon, Jae Kyu Suhr, Ho Gi Jung
  • Publication number: 20160123428
    Abstract: A gear train layout structure may include a fuel pump configured to pressurize fuel and to supply the pressurized fuel to an engine, a pump shaft, a driven gear for rotating the pump shaft, a driving gear to drive the driven gear, a first balance shaft and a second balance shaft respectively mounted at a front and a rear of a crankshaft of the engine for balancing the engine and attenuating vibration of the engine, a first balance gear and a second balance gear, a crank gear fixedly mounted on a side portion of the crankshaft, and at least one connecting rod connecting the crankshaft and a piston for rotating the crankshaft.
    Type: Application
    Filed: May 28, 2015
    Publication date: May 5, 2016
    Applicant: Hyundai Motor Company
    Inventors: Jae Kyu Lee, Ahn Lee, Se Eun Kim
  • Publication number: 20160125588
    Abstract: An apparatus for recognizing a position of an obstacle in a vehicle obtains image data and ultrasonic sensor data through a camera and an ultrasonic sensor, detects linear edges perpendicular to a ground surface in the image data, detects a discontinuous position at which the ultrasonic sensor data are not continuous, detects intersection points of the linear edges detected in continuous images from the image data when the discontinuous position coincides with a camera position, and estimates the intersection points to be the position of the obstacle.
    Type: Application
    Filed: June 18, 2015
    Publication date: May 5, 2016
    Inventors: Jae Seob CHOI, Seong Sook RYU, Dae Joong YOON, Jin Wook CHOI, Eu Gene CHANG, Ho Gi JUNG, Jae Kyu SUHR
  • Patent number: 9324382
    Abstract: A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: April 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Seok Suh, Jae-kyu Lee
  • Publication number: 20160111360
    Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 21, 2016
    Inventors: Jae Kyu CHO, Shan GAO
  • Patent number: 9318599
    Abstract: A power semiconductor device may include: a first conductive type drift layer in which trench gates are formed; a second conductive type well region formed on the drift layer so as to contact the trench gate; a first conductive type source region formed on the well region so as to contact the trench gate; and a device protection region formed below a height of a lowermost portion of the source region in a height direction.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: April 19, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Kyu Sung, Jae Hoon Park, Kee Ju Um, In Hyuk Song
  • Patent number: 9301969
    Abstract: The present invention relates to a pharmaceutical composition for preventing or treating neurodegenerative diseases by targeting a specific miRNA. In addition, the present invention relates to a kit for diagnosing neurodegenerative diseases. A miR-206 target found in the present invention, which is highly expressed in both animal models of Alzheimer's disease and human brain samples, is a substantial treatment target selected without artifact errors. An antisense oligonucleotide of the present invention as an inhibitor for miR-206 suggests a successful result in treatment of neurodegenerative diseases by targeting miRNA. The antisense oligonucleotide of the present invention inhibits the function of miR-206 to greatly increase the levels of BDNF and IGF-1 and to increase the regeneration of synapses, thereby treating neurodegenerative diseases, particularly Alzheimer's disease.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: April 5, 2016
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae-Kyu Roh, Sang Kun Lee, Man Ho Kim, Kon Chu, Keun-Hwa Jung, Soon-Tae Lee
  • Patent number: 9293976
    Abstract: A stepping motor includes a housing, a stator assembly, a rotor, and a sensor portion. The stator assembly is disposed inside the housing. The rotor is rotatably disposed inside the stator assembly and includes a rotation shaft, and opposite ends of the rotation shaft are supported by the housing. The sensor portion is disposed inside the housing and detects a magnetic field of the rotor.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kun-woo Lee, Jae-kyu Shim, Woo-jong Cho, Bon-min Koo
  • Publication number: 20160079839
    Abstract: A step motor includes a plurality of stator cores. Each of the stator cores have a coil unit coiled therearound. The step motor includes a rotor that includes a rotation shaft and a plurality of permanent magnets and is configured to rotate by magnetic interaction between the stator cores and the permanent magnets. The step motor also includes a plurality of conducting parts on one cross-sectional surface of the rotor. The step motor further includes a printed circuit board (PCB) including electric elements that are arranged at certain positions and are disposed to face the conducting parts. The conducting parts and the electric elements are configured to electrically or magnetically interact as the rotor rotates to change electrical signals generated by the electric elements.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 17, 2016
    Inventors: Jae-kyu Shim, Woo-jong Cho, Bon-min Koo
  • Patent number: 9281344
    Abstract: The magnetic memory device includes a plurality of source lines arranged in parallel in a second direction orthogonal to a first direction while extending in the first direction on a substrate, a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate, a plurality of bit lines arranged in parallel in the second direction while extending in the first direction on the substrate to alternate with the plurality of source lines, and a plurality of active regions arranged to extend at an oblique angle with respect to the first direction and arranged so that one memory cell is selected when one of the plurality of word lines and one of the plurality of source lines or the plurality of bit lines are selected.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-kyu Lee, Ki-Seok Suh
  • Publication number: 20160063942
    Abstract: A voltage converter includes a conversion unit, a self driver and an output unit. The conversion unit includes at least one inductor and provides a boosting power based on an input voltage and a first driving signal. The self driver includes at least one inductor that forms a magnetic coupling with the at least one inductor of the conversion unit. The self driver generates a second driving signal that is synchronized with the first driving signal through the magnetic coupling. The output unit generates an output voltage based on the boosting power and the second driving signal. Switching loss and conduction loss may be reduced by replacing an output diode with an output transistor and voltage spike and electromagnetic interference may be reduced through zero voltage switching. The driving signal of the output transistor may be controlled efficiently by adjusting the inductance of the driving inductor.
    Type: Application
    Filed: February 9, 2015
    Publication date: March 3, 2016
    Inventors: Gwang-Teak LEE, Seung-Young CHOI, Jae-Kyu PARK
  • Patent number: 9267115
    Abstract: The present invention relates to novel hydrogenases isolated from novel hyperthermophilic strains belonging to Thermococcus spp., genes encoding the hydrogenases, and methods of producing hydrogen using strains having the genes. According to the hydrogen production methods of the invention, a large amount of hydrogen can be produced merely by culturing the strains in specific culture conditions. Thus, the methods of the invention have advantages in that they are more economic and efficient than existing hydrogen production methods and can produce hydrogen even at high temperature.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: February 23, 2016
    Assignee: KOREA OCEAN RESEARCH & DEVELOPMENT INSTITUTE
    Inventors: Jung Hyun Lee, Sung Gyun Kang, Hyun Sook Lee, Sang Jin Kim, Kae Kyoung Kwon, Sun Shin Cha, Jung Ho Jeon, Yona Cho, Yun Jae Kim, Seung Seop Bae, Jae Kyu Lim, In Soon Jeong
  • Patent number: 9261719
    Abstract: A liquid crystal shutter includes: a first plate including a first transparent electrode layer, a second plate disposed parallel to the first plate and including a second transparent electrode layer, a liquid crystal layer disposed between the first plate and the second plate and is configured to transmit or block light according to a first potential difference between the first transparent electrode layer and the second transparent electrode layer, and a heating electrode configured to generate a second potential difference for generating heat in the first transparent electrode layer.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-kyu Shim, Bon-min Koo, Yu-kyung Ham, Kun-woo Lee, Woo-jong Cho