Abstract: In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.

Abstract: A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the semiconductor substrate on both sides of the recess holes. Gate lines are formed to overlie and extend across the channel fins. Source/drain regions are formed at both ends of the channel fins and connected by the channel fins. Other embodiments are described and claimed.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.

Abstract: A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.

Abstract: According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

Abstract: A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

Abstract: A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom interlayer insulating film, and an etching stopper between the upper and bottom interlayer insulating layers that protrudes into the storage node contact; forming a first conductive film for a storage node on the substrate; forming a second insulating film where a portion of a surface corresponding to the storage node contact is recessed; forming an etching mask layer on the recessed portion of the second insulating film; etching the second insulating film using the etching mask layer; forming a second conductive film for a storage node on the substrate; etching the first and second conductive films to isolate nodes; and removing the etching mask layer, the second insulating film and the upper interlayer insulating film.

Abstract: A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom interlayer insulating film, and an etching stopper between the upper and bottom interlayer insulating layers that protrudes into the storage node contact; forming a first conductive film for a storage node on the substrate; forming a second insulating film where a portion of a surface corresponding to the storage node contact is recessed; forming an etching mask layer on the recessed portion of the second insulating film; etching the second insulating film using the etching mask layer; forming a second conductive film for a storage node on the substrate; etching the first and second conductive films to isolate nodes; and removing the etching mask layer, the second insulating film and the upper interlayer insulating film.

Abstract: First and second epitaxial layers are spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the substrate, and extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap. First and second impurity regions are contained at least partially within the first and second epitaxial layers, respectively, and a gate insulating layer is located between the gate electrode and the semiconductor substrate. A non-planar channel region may be defined within the portions of the first and second epitaxial layers which are overlapped by the gate electrode and within a surface portion the semiconductor substrate located between the first and second epitaxial layers.

Abstract: First and second epitaxial layers are spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the substrate, and extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap. First and second impurity regions are contained at least partially within the first and second epitaxial layers, respectively, and a gate insulating layer is located between the gate electrode and the semiconductor substrate. A non-planar channel region may be defined within the portions of the first and second epitaxial layers which are overlapped by the gate electrode and within a surface portion the semiconductor substrate located between the first and second epitaxial layers.

Abstract: First and second epitaxial layers are spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the substrate, and extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap. First and second impurity regions are contained at least partially within the first and second epitaxial layers, respectively, and a gate insulating layer is located between the gate electrode and the semiconductor substrate. A non-planar channel region may be defined within the portions of the first and second epitaxial layers which are overlapped by the gate electrode and within a surface portion the semiconductor substrate located between the first and second epitaxial layers.

Abstract: First and second epitaxial layers are spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the substrate, and extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap. First and second impurity regions are contained at least partially within the first and second epitaxial layers, respectively, and a gate insulating layer is located between the gate electrode and the semiconductor substrate. A non-planar channel region may be defined within the portions of the first and second epitaxial layers which are overlapped by the gate electrode and within a surface portion the semiconductor substrate located between the first and second epitaxial layers.