Abstract: A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.

Abstract: A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the exter

Abstract: An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.

Abstract: A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.

Abstract: A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

Abstract: An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage.

Abstract: A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

Abstract: A duty cycle correction circuit capable of reducing current consumption and that includes a back-bias voltage supply circuit for supplying back-bias voltages, wherein a duty cycle of an input clock is reflected on the back-bias voltages; and a buffer for adjusting the duty cycle of the input clock and configured to receive the back-bias voltages.

Abstract: A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.