Abstract: The quantum dot comprises a ligand which is a copolymer comprising a first repeating unit comprising at least one or more hole transporting functional groups and a second repeating unit comprising at least one or more photocrosslinking functional groups.

Abstract: A phase locked loop circuit and a semiconductor device are provided. The phased locked loop circuit includes a reference current generator configured to generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and output the summed compensation current as a reference current, a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code and a voltage control oscillator configured to generate a signal based on the control current, wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.

Abstract: A chip-on-film package includes: a lower base film including a first surface and a second surface, which are opposite to each other; an upper base film including a third surface and a fourth surface, which are opposite to each other, and is disposed on the lower base film; a first semiconductor chip mounted on the second surface of the lower base film; a second semiconductor chip mounted on the third surface of the upper base film; and an interposer film interposed between the lower and upper base films, wherein the second and third surfaces face each other.

Abstract: A light device including a substrate, and first and second light emitters spaced apart from each other, and a power source to control the first light emitter and the second light emitter, in which the first and second light emitters include a light emitting region, a wavelength conversion layer disposed on the light emitting region, and a lateral reflection layer covering a region of a side of the light emitting region and the wavelength conversion layer, the first light emitter and the second light emitter are configured to output the same or different magnitudes of power by receiving the same or different magnitudes of current, the first and second light emitters are respectively configured to emit first light and second light, the first light emitter is electrically connected to the second light emitter through a common electrode.

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Abstract: A data receiving device may include a dummy stage block. The dummy stage block may include m dummy stages, wherein m is a natural number greater than or equal to two. Each of the m dummy stages may be configured to remove inter-symbol interference (ISI) from a dummy input signal using dummy coefficient information to generate a dummy output signal free of the ISI. Each of the m dummy stages may be further configured to output the dummy output signal. A normal stage block may include n normal stages, wherein n is a natural number greater than or equal to two. Each of the n normal stages may be configured to remove ISI from an input signal using coefficient information to generate an output signal free of the ISI and may be further configured to output the output signal.

Abstract: A semiconductor package includes a film substrate; a wiring layer provided on the film substrate; and a semiconductor chip provided on the wiring layer and electrically connected to the wiring layer. The film substrate includes a first layer, wherein the first layer is an insulating layer having the wiring layer thereon. The film substrate further includes a second layer, wherein the second layer is attached to a bottom of the first layer and comprises a gas. The second layer is configured to be peeled off of the first layer.

Abstract: According to the present invention, it is possible to provide a composition comprising a resin component and a filler component comprising a filler having a specific gravity of 3 or more and a filler having a specific gravity of less than 3, which achieves a low specific gravity effect in a state where a filler is filled in a high content and in a state where realization of physical properties is sufficiently secured, and has improved storage stability without deterioration of physical properties such as a thermal conductivity, and a product comprising a heating element and the composition or a cured product thereof in thermal contact with the heating element.

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

Abstract: A semiconductor package includes a base film having a first mount section, a first folding section, a second folding section, and a second mount section. A first semiconductor chip is disposed on the first mount section of the base film. A second semiconductor chip is disposed on the second mount section of the base film. Test pads are disposed on the first or second folding sections of the base film and is connected to each of the first and second semiconductor chips. Connection pads are disposed on the first or second mount sections of the base film and are connected to each of the first and second semiconductor chips. The first and second folding sections vertically overlap each other. The test pads are interposed between and buried by the first and second folding sections.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a circuit substrate, a semiconductor chip mounted on the circuit substrate, and a thermal radiation film covering the semiconductor chip on the circuit substrate. The semiconductor chip includes first lateral surfaces opposite to each other in a first direction and second lateral surfaces opposite to each other in a second direction that intersects the first direction. A first width of the first lateral surface is less than a second width of the second lateral surface. The thermal radiation film covers a top surface of the semiconductor chip and entirely surrounds the first and second lateral surfaces of the semiconductor chip. The thermal radiation film has slits directed toward the first lateral surfaces from ends of the thermal radiation film.

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Abstract: Disclosed is an apparatus and method for updating a current pattern for rapid charging, and a computer program stored in a storage medium performing the method, the apparatus includes a resistance calculation unit for calculating an internal resistance of a battery module, a storage unit for storing a current pattern for rapid charging of the battery module, and a calculation unit for updating the current pattern according to a state of the internal resistance of the battery module, and the calculation unit calculates a resistance increase rate based on the calculated internal resistance, calculates an adjustment coefficient based on the calculated resistance increase rate, and updates the current pattern using the calculated adjustment coefficient and the current pattern so that when performing rapid charging, an impact on the battery module life is minimized.

Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

Abstract: The present invention relates to a composition for preventing, improving and treating an inflammatory macrophage-mediated autoimmune disease, including a stem cell-derived exosome surface-modified with a sugar compound to target an activated macrophage, and the composition according to the present invention may specifically target an activated macrophage to increase the therapeutic efficiency for various types of autoimmune diseases including rheumatoid arthritis. In addition, the composition according to the present invention has a more excellent therapeutic effect and minimizes side effects compared with conventional antiinflammatory agents, stem cell therapeutic agents or exosomes because it contains a gene, protein or growth factor related to the proliferation, differentiation and regeneration of stem cells, and does not include an antibiotic or serum, or harmful factors of the cell culture.

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.