Abstract: A wafer level stack package according to the present invention has upper and lower semiconductor chips stacked together in a wafer level. Each chip has a first face where bond pads are formed and an opposite second face. The first faces confront each other in a stack. In each chip, metal patterns are connected to the bond pads and intervene between insulating layers. Through holes are formed at both sides of the upper chip, and a pattern film is adhered to the second face of the upper chip. The metal patterns are exposed in the through holes and electrically connected to solder balls on the pattern film. A related method is also provided.

Abstract: Disclosed are a chip size stack package, a memory module having the same and a method for fabricating the memory module. In the chip size stack package, two semiconductor chips are arranged in a manner such that their surfaces on which bonding pads are formed, are opposed to each other at a predetermined interval. Insulating layers are applied to the surfaces of the semiconductor chips on which surfaces the bonding pads are formed, in a manner such that the bonding pads are exposed. Metal traces are respectively deposited on the insulating layers and connected to the bonding pads. Solder balls electrically connect the metal traces with each other. One ends of metal wires are bonded to a side of one of the metal traces. Both sides of the semiconductor chips and a space between them are molded by an encapsulate, in a manner such that the other ends of the metal wires are exposed.

Abstract: Disclosed is a multi-chip package. According to the present invention, a first semiconductor chip includes a first face in which a bonding pad disposed, and a second face opposite to the first face. A first insulating layer is coated over the first face of the first semiconductor chip so as to expose the bonding pad. A metal pattern is deposited on the first insulating layer and one end of the metal pattern is connected to the exposed bonding pad. A second insulating layer having a via hole exposing the metal pattern and a ball land, is coated over the first face of the first semiconductor chip. A second semiconductor chip includes a first face in which a bonding pad is disposed and opposite to the first face of the first semiconductor chip, and a second face opposite to the first face of the second semiconductor chip. The second semiconductor chip is opposed from the first face of the first semiconductor chip by a selected distance.