Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A portable terminal includes a touch screen capable of performing a character input method according to a touch event. The character input method in a terminal having a touch screen, includes: checking and displaying a character mapped to a sensed region of a first touch event when the first touch event is sensed in a character input mode, and determining whether the first touch event is released; determining whether the first touch event is moved when the first touch event is not released; and confirming a moving direction of the first touch event and adding a vowel to display a character when the first touch event is moved.

Abstract: A character input method and apparatus for a terminal. The character input method includes displaying a main keypad including a plurality of main keys in text input mode. The method also includes entering, when a touch is detected at one of the main keys, a character assigned to the main key at which the touch is made. The method further includes displaying a sub keypad around the main key, the sub keypad including a plurality of sub keys assigned characters combinable with the entered character. The method also includes entering, when the touch is dragged to one of the sub keys, the character assigned to the sub key to which the touch is dragged. The character input method and apparatus of the present disclosure are advantageous for the user to input characters using the main and sub keypads displaying characters combinable with each other.

Abstract: A key input method and apparatus allow efficient typing on a keypad. A pressing of a first key followed by a pressing of a second key is detected. One of input values corresponding to one of the first and second keys is selected according to the other key of the first and second keys. The selected input value is entered as a key input.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Abstract: A remote control device capable of being separated into two or more parts is provided. The remote control device includes a first remote controller, and a second remote controller which is capable of being connected to or separated from the first remote controller. If the first remote controller and the second remote controller are connected, the first remote controller and the second remote controller may function as a single unit, or if not, the first remote controller and the second remote controller may function as individual units.

Abstract: A semiconductor memory device having internal circuits responsive to temperature data, in order to compensate an output characteristic change of the internal circuits and reduce power consumption depending on temperature change, and method thereof are disclosed. The semiconductor memory device may include a temperature sensing circuit and an internal circuit. The temperature sensing circuit may generate and output temperature data in response to ambient temperature of the semiconductor memory device. The internal circuit may adjust an output level of an output signal in response to the temperature data from the temperature sensing circuit.

Abstract: A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: Semiconductor memory devices having hierarchical word line structures are provided in which sub-word line driver circuitry is designed with layout patterns that enable increased integration density and high performance operation.

Abstract: The present invention relates to novel derivatives of oxazolidinone, a method thereof and pharmaceutical compositions comprising the derivatives for use in an antibiotic. The oxazolidinone derivatives of the present invention show inhibitory activity against a broad spectrum of bacteria and lower toxicity. The prodrugs, prepared by reacting the compound having hydroxyl group with amino acid or phosphate, have an excellent efficiency on solubility thereof against water. Further, the derivatives of the present invention may exert potent antibacterial activity versus various human and animal pathogens, including Gram-positive bacteria such as Staphylococi, Enterococci and Streptococi, anaerobic microorganisms such as Bacteroides and Clostridia, and acid-resistant microorganisms such as Mycobacterium tuberculosis and Mycobacterium avium. Accordingly, the compositions comprising the oxazolidinone are used in an antibiotic.

Abstract: A method for manufacturing an engine intake manifold assembly is provided. The method includes forming a top, middle, and bottom section of the manifold assembly in an injection molding process, each including cavities defined with positive draft angles, the cavities defining a plurality of internal passageways in an assembled state of the manifold assembly. The top, middle, and bottom sections are joined to form the manifold assembly through vibration welding or ultrasonic welding. An engine intake manifold assembly having top, middle, and bottom sections joined through vibration welding or ultrasonic welding is also provided.

Abstract: An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Abstract: A semiconductor memory device having internal circuits responsive to temperature data, in order to compensate an output characteristic change of the internal circuits and reduce power consumption depending on temperature change, and method thereof are disclosed. The semiconductor memory device may include a temperature sensing circuit and an internal circuit. The temperature sensing circuit may generate and output temperature data in response to ambient temperature of the semiconductor memory device. The internal circuit may adjust an output level of an output signal in response to the temperature data from the temperature sensing circuit.

Abstract: In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

Abstract: An external high/low voltage compatible semiconductor memory device includes an internal voltage pad, an internal voltage generation circuit, and an internal voltage control signal generation circuit. The internal voltage pad connects a low external voltage with an internal voltage, and the internal voltage generation circuit generates an internal voltage in response to an internal voltage control signal and a high external voltage. The internal voltage control signal generation circuit generates an internal voltage control signal according to an high or low external voltage. Thus, a database of the semiconductor memory device can be managed without classifying the database into databases for the high voltage and databases for the low voltage because of the internal voltage control signal. In addition, the internal voltage level is stable because charges provided to the internal voltage are regulated according to a voltage level of the external voltage.

Abstract: In this circuit, an external voltage source is supplied or down converted in response to a normal operating mode to provide the internal voltage source of a first level to the internal circuit. The external voltage source is converted to a voltage of a second level, lower than the first level, in response to a low consumption power mode having a complementary relation with the normal mode.

Abstract: Semiconductor devices and methods of sampling data therefrom are provided in which data is sampled from a memory cell array based on a relative position of a memory cell array section that contains the data. A sense amplifier generates an output signal in response to an address of one or more cells in a memory cell array. A control circuit generates a sample control signal in response to at least a portion of the address (e.g., one or more high order bits of the address) of the one or more cells in the memory cell array. A data sampling circuit then samples the output signal of the sense amplifier in response to the sample control signal. The portion of the memory cell array address used to drive the control circuit may logically divide the memory cell array into two or more sections. The control circuit may adjust the timing of the sample control signal in accordance with the proximity of a memory cell array section to the sense amplifier.

Abstract: Output drivers preferably contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits may include first and second control signal lines (e.g., MRS1, MRS2), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS1) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS2) and a second control input. First and second complementary control signals lines (e.g.