Abstract: A stacked type falling film evaporator includes a first evaporator, a second evaporator, a first vapor recovering device, a second vapor recovering device and a vapor recompressor. The first evaporator and the second evaporator respectively have evaporation tubes of a length of 5 m to 10 m, and are stacked in such a manner that wastewater passes through the first evaporator and the second evaporator in order. The first vapor recovering device collects vapor generated from the wastewater in the first evaporator and supplies the collected vapor to the second evaporator. The second vapor recovering device collects vapor generated from the wastewater in the second evaporator and supplies the collected vapor to the first evaporator. The vapor recompressor compresses the vapor collected in the second vapor recovering device before the vapor is supplied to the first evaporator.

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Abstract: A stacked type falling film evaporator includes a first evaporator, a second evaporator, a first vapor recovering device, a second vapor recovering device and a vapor recompressor. The first evaporator and the second evaporator respectively have evaporation tubes of a length of 5 m to 10 m, and are stacked in such a manner that wastewater passes through the first evaporator and the second evaporator in order. The first vapor recovering device collects vapor generated from the wastewater in the first evaporator and supplies the collected vapor to the second evaporator. The second vapor recovering device collects vapor generated from the wastewater in the second evaporator and supplies the collected vapor to the first evaporator. The vapor recompressor compresses the vapor collected in the second vapor recovering device before the vapor is supplied to the first evaporator.

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Abstract: An electric toothbrush of the present invention includes: a case having first and second drive shafts exposed therefrom, the first and second drive shafts being rotated in opposite directions and moved forward and backward respectively by a drive unit which is driven by a motor; first and second toothbrush bodies coupled to the first and second drive shafts by first and second coupling units respectively, so as to transmit the rotational force and forward and backward motions of the first and second drive shafts; a brush installed at the ends of the first and second toothbrush bodies so as to clean teeth by the rotational force and forward and backward motions transmitted to the first and second toothbrush bodies; and a third toothbrush body having an auxiliary brush, which is coupled to a third drive shaft of the drive unit installed in the case.

Abstract: A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.

Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array receives a first power supply voltage and includes a plurality of bit cells that store data based on the first power supply voltage. The peripheral circuit is receives a second power supply voltage and controls the memory cell array based on the second power supply voltage. The peripheral circuit includes a voltage generation circuit that receives the first power supply voltage and the second power supply voltage. The voltage generation circuit adaptively adjusts a word-line driving voltage directly or indirectly based on a difference between the first power supply voltage and the second power supply voltage during a memory operation on the plurality of bit cells, and applies the word-line driving voltage to a first word-line coupled to first bit cells selected from the bit cells.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

Abstract: A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.

Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.

Abstract: An integrated circuit, a method of controlling an operation timing of a memory device, an application processor, and a power manager are provided. The application processor includes: a power manager configured to determine a first operating power level, from among a plurality of operating power levels, to determine a first timing margin corresponding to the first operating power level, to generate a first gray code signal indicating the first timing margin, and to output the first gray code signal; and a first memory device configured to adjust an operation timing according to the first timing margin indicated by the first gray code signal, wherein the power manager is configured to provide the first operating power level to the first memory device.

Abstract: A control method of a home appliance, the method including retrieving information about a communication device, authenticating the communication device, registering the authenticated communication device, receiving voice data from the registered communication device, outputting a voice signal corresponding to the received voice data to a user, receiving the voice signal from the user, and transmitting voice data corresponding to the received voice signal to the communication device. When the method is used, even if a user loses a communication device in a home, call is possible using a home appliance such as refrigerator.

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

Abstract: A control method of a home appliance, the method including retrieving information about a communication device, authenticating the communication device, registering the authenticated communication device, receiving voice data from the registered communication device, outputting a voice signal corresponding to the received voice data to a user, receiving the voice signal from the user, and transmitting voice data corresponding to the received voice signal to the communication device. When the method is used, even if a user loses a communication device in a home, call is possible using a home appliance such as refrigerator.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: A display apparatus comprising: a flexible display panel including a display view area and a dummy area around the display view area, wherein the flexible display panel are bended at least on the display view area; a polarizing plate disposed over the display view area of the flexible display panel and between the flexible display panel and a protective panel; the protective panel disposed over the polarizing plate; and a step coverage base disposed over the dummy area of the flexible display panel, alongside to the polarizing plate.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.