Abstract: A Liquid Crystal Display (LCD) module for use in a portable terminal is provided. The LCD module includes a reinforcement plate of a metal material having a bottom surface, and a side surface bent and extended at a substantially constant height along an edge from the bottom surface, a backlight unit laminated onto an upper part of the reinforcement plate, and having a frame of a synthetic resin material that is formed along an edge to insert-mold the reinforcement plate, and an LCD panel fixed by a double sided tape at an upper part of the backlight unit. A portion of the side surface of the reinforcement plate is sequentially twice bent back onto itself on the outside of the reinforcement plate such that its end has a substantially constant width in contact with the bottom surface of the reinforcement plate.

Abstract: A method for forming patterns in a semiconductor memory device, wherein first spacers arranged at a first spacing and second spacers arranged at a second spacing are formed on a target layer which is formed on a semiconductor substrate. A mask pattern is formed to cover a portion of the target layer defined by the two adjacent second spacers. At least two first patterns and at least one second pattern is formed by patterning the target layer using the first spacers, the second spacers and the mask pattern as an etch mask. Here, the second pattern is wider than the first pattern.

Abstract: A method of correcting an optical proximity effect may include the steps of: fabricating a test mask having test patterns; projecting patterns on a wafer using the test mask; measuring line widths of the patterns formed on the wafer; and executing a model calibration using the measured line widths and writing a correction recipe. The entire area of the wafer chip may be divided into a plurality of templates. An optical proximity correction may be executed on one of the templates and it may be verified that the optical proximity correction was executed properly on another template. The data for the templates that pass a verification may be merged and final data may be written using the merged data. A photomask may be fabricated using the final data.

Abstract: A pattern decomposition method capable of achieving patterns with a complicated layout by double exposure. The pattern decomposition method for decomposing a target pattern which includes first patterns having repeated lines and spaces and second patterns disposed between the first patterns and having a predetermined size into patterns for first exposure and patterns for second exposure, comprises decomposing the first patterns into a pattern for first exposure and a pattern for second exposure, decomposing the second patterns into a pattern for first exposure and a pattern for second exposure, and respectively merging the pattern for first exposure or the pattern for second exposure of the first patterns with the pattern for first exposure or the pattern for second exposure of the second patterns.

Abstract: The present invention is the thing about exposure mask and manufacturing method of semiconductor device using the same It is the technology which forms the semiconductor device and makes the high integration possible by using the exposure mask including with the cell array having the light blocking patterns of line-shape and includes the assistant pattern assist feature, AF field of the same direction as the cell array.

Abstract: A double exposure method forms first and second patterns on a cell region and a peripheral circuit region of a wafer, respectively. The method comprises performing a primary exposure through two-beam imaging of 0 order light and ?1 order light or +1 order light using a photomask to form the first pattern, and performing a secondary exposure through three-beam imaging of the 0 order light and ±1 order light using the photomask to form the second pattern. Since the double exposure method is performed using the single photomask together with different illuminating systems, exposure time and the number of exposures are both decreased, thereby simplifying the overall process of manufacturing a semiconductor device.

Abstract: A display apparatus of a portable terminal are provided that includes a light source for generating and outputting internal light; a display device for receiving the internal light from the light source through its one side and refracting the incident internal light to its upper side; and a display mirror layer. The display mirror layer includes a half mirror layer for receiving the internal light refracted by the display device and allowing it to pass therethrough to the outside; and a flange mirror layer for receiving the internal light from the light source and reflecting it. The display apparatus is configured in such a way that a display mirror layer is placed between the display device and the display window, so that it can enhance the clarity of images displayed on the display area and improve the appearance of the portable terminal.

Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.

Abstract: A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a first patterning process are not additionally blocked, and the oxide film is used as an etching barrier to obtain an accurate overlay between patterns and improve CD uniformity, thereby improving a characteristic of the device.

Abstract: A method for forming patterns in a semiconductor memory device, wherein first spacers arranged at a first spacing and second spacers arranged at a second spacing are formed on a target layer which is formed on a semiconductor substrate. A mask pattern is formed to cover a portion of the target layer defined by the two adjacent second spacers. At least two first patterns and at least one second pattern is formed by patterning the target layer using the first spacers, the second spacers and the mask pattern as an etch mask. Here, the second pattern is wider than the first pattern.

Abstract: A method of correcting an optical proximity effect may include the steps of: fabricating a test mask having test patterns; projecting patterns on a wafer using the test mask; measuring line widths of the patterns formed on the wafer; and executing a model calibration using the measured line widths and writing a correction recipe. The entire area of the wafer chip may be divided into a plurality of templates. An optical proximity correction may be executed on one of the templates and it may be verified that the optical proximity correction was executed properly on another template. The data for the templates that pass a verification may be merged and final data may be written using the merged data. A photomask may be fabricated using the final data.

Abstract: A pattern decomposition and optical proximity correction method for double exposure comprises defining second exposure patterns by performing a logical operation on target patterns and first exposure patterns, comparing the first and second exposure patterns with the target patterns by performing a logical operation on the first and second exposure patterns, performing optical proximity correction on the first exposure patterns to form fourth exposure patterns, performing the optical proximity correction on the second exposure patterns to form fifth exposure patterns, and comparing the fourth and fifth exposure patterns with the target patterns by performing a logical operation on the fourth and fifth exposure patterns.

Abstract: A pattern decomposition method capable of achieving patterns with a complicated layout by double exposure. The pattern decomposition method for decomposing a target pattern which includes first patterns having repeated lines and spaces and second patterns disposed between the first patterns and having a predetermined size into patterns for first exposure and patterns for second exposure, comprises decomposing the first patterns into a pattern for first exposure and a pattern for second exposure, decomposing the second patterns into a pattern for first exposure and a pattern for second exposure, and respectively merging the pattern for first exposure or the pattern for second exposure of the first patterns with the pattern for first exposure or the pattern for second exposure of the second patterns.

Abstract: A pattern decomposition and optical proximity correction method for double exposure comprises defining second exposure patterns by performing a logical operation on target patterns and first exposure patterns, comparing the first and second exposure patterns with the target patterns by performing a logical operation on the first and second exposure patterns, performing optical proximity correction on the first exposure patterns to form fourth exposure patterns, performing the optical proximity correction on the second exposure patterns to form fifth exposure patterns, and comparing the fourth and fifth exposure patterns with the target patterns by performing a logical operation on the fourth and fifth exposure patterns.

Abstract: An SRAM employs a virtual rail configuration that is stable against process-voltage-temperature (PVT) variation. The SRAM provides a virtual power supply voltage to an SRAM cell that is obtained by lowering a power supply voltage by a threshold voltage of a transistor and a virtual ground voltage obtained by raising a ground voltage by a threshold voltage of a transistor. Due to the use of PMOS and NMOS transistors of diode types connected between the power supply voltage and the virtual power supply voltage and the use of NMOS and PMOS transistors of diode types connected between the ground voltage and the virtual ground voltage, a virtual power supply voltage level and a virtual ground voltage level that are stable even against various PVT variations are provided, so that low-leakage current characteristics are stable.

Abstract: Disclosed is a method of making a semiconductor device in which a main pattern is formed through a photolithography process over a low-density pattern area having a relatively small number of patterns to be formed in certain areas as compared to the other areas. According to the method at least one or more dummy patterns are formed over the active areas, where the main pattern is formed, and adjacent inactive areas are spaced a predetermined distance from the sides of the main pattern. This method can improve the process margin and improve the uniformity of critical regions of patterns to thus improve the yield of a semiconductor device by making a low-density pattern area with the same pattern density as high-density or intermediate-density pattern areas by forming dummy patterns, which do not affect the semiconductor device, on the sides of a main pattern of the low-density pattern area according to a design rule.

Abstract: An SRAM employs a virtual rail configuration that is stable against process-voltage-temperature (PVT) variation. The SRAM provides a virtual power supply voltage to an SRAM cell that is obtained by lowering a power supply voltage by a threshold voltage of a transistor and a virtual ground voltage obtained by raising a ground voltage by a threshold voltage of a transistor. Due to the use of PMOS and NMOS transistors of diode types connected between the power supply voltage and the virtual power supply voltage and the use of NMOS and PMOS transistors of diode types connected between the ground voltage and the virtual ground voltage, a virtual power supply voltage level and a virtual ground voltage level that are stable even against various PVT variations are provided, so that low-leakage current characteristics are stable.

Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.

Abstract: Disclosed is a nonvolatile memory device comprising a semiconductor substrate defining first and second active regions arranged in one direction; a first gate insulating layer and a floating gate deposited on the first and second active regions in a predetermined pattern; a second gate insulating layer and a control gate line deposited in one direction perpendicular to the first and second active regions and covering the floating gate; first impurity regions formed in the first and second active regions at one side of the control gate line; second impurity regions formed in the first and second active regions at other side of the control gate line; first contact plugs contacted with the first impurity regions; and a common conductive line formed in one direction on the semiconductor substrate at the other side of the control gate line, for connecting the second impurity regions of the first and second active regions.

Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.