Patents by Inventor Jae Sung Sim

Jae Sung Sim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220408559
    Abstract: A printed circuit board includes: a first insulating layer; a first metal layer disposed on one surface of the first insulating layer; a second metal layer disposed on the other surface facing the one surface of the first insulating layer; a via penetrating through the first insulating layer to connect the first and second metal layers to each other; and a heterogeneous metal region disposed in at least one of an area in which the via is adjacent to the first insulating layer and an area in which the via is adjacent to the first metal layer, and including a material different from that of the via, wherein the heterogeneous metal region includes at least one of nickel (Ni), silicon (Si), and titanium (Ti).
    Type: Application
    Filed: March 7, 2022
    Publication date: December 22, 2022
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hee-Joon CHUN, Jae Sung SIM, Hak Young LEE, Kwang Hee KWON, Hee Jung JUNG
  • Publication number: 20220210921
    Abstract: A connection structure-embedded substrate includes: a printed circuit board including a plurality of first insulating layers of which at least one has a cavity provided therein, a plurality of first wiring layers disposed as at least one of an outer portion and an inner portion of the plurality of first insulating layers, and a first build-up insulating layer disposed on an upper surface of the plurality of first insulating layers; and a connection structure at least partially disposed in the cavity. The first build-up insulating layer is disposed in the cavity, and each of a lower surface of the connection structure and a lower surface of the cavity is in contact with at least a portion of the first build-up insulating layer, respectively.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 30, 2022
    Inventors: Ho Hyung HAM, Won Seok LEE, Jae Sung SIM
  • Publication number: 20220180951
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Applicant: SK hynix Inc.
    Inventors: Sung Hoon CHO, Jae Sung SIM, Han Soo JOO, Hee Chang CHAE, Se Kyoung CHOI
  • Patent number: 11335406
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: May 17, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Hoon Cho, Jae Sung Sim, Se Kyoung Choi
  • Patent number: 11302404
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: April 12, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Hoon Cho, Jae Sung Sim, Han Soo Joo, Hee Chang Chae, Se Kyoung Choi
  • Publication number: 20210366550
    Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.
    Type: Application
    Filed: October 20, 2020
    Publication date: November 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Sung Hoon CHO, Jae Sung SIM, Se Kyoung CHOI
  • Patent number: 11152390
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Publication number: 20210241838
    Abstract: Provided herein may be a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device may include: a memory block including upper pages, a center page, and lower pages; a peripheral circuit configured to perform a read operation on the memory block; and a control logic configured to control the peripheral circuit to perform the read operation and control the peripheral circuit such that, during the read operation, based on a location of a selected page among the plurality of pages, a pass voltage to be applied to first adjacent pages disposed adjacent to the selected page in a first direction differs from a pass voltage to be applied to second adjacent pages disposed adjacent to the selected page in a second direction.
    Type: Application
    Filed: July 8, 2020
    Publication date: August 5, 2021
    Applicant: SK hynix Inc.
    Inventors: Sung Hoon CHO, Jae Sung SIM, Han Soo JOO, Hee Chang CHAE, Se Kyoung CHOI
  • Patent number: 11076488
    Abstract: A board having an electronic component embedded therein, includes a core layer having a groove with a bottom surface, an electronic component disposed above the bottom surface of the groove and spaced apart from the bottom surface of the groove, and an insulating layer disposed on the core layer and covering at least a portion of the electronic component. The insulating layer is disposed in at least a portion of a space between the bottom surface of the groove and the electronic component.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Hyung Ham, Jae Sung Sim
  • Publication number: 20210068259
    Abstract: A board having an electronic component embedded therein, includes a core layer having a groove with a bottom surface, an electronic component disposed above the bottom surface of the groove and spaced apart from the bottom surface of the groove, and an insulating layer disposed on the core layer and covering at least a portion of the electronic component. The insulating layer is disposed in at least a portion of a space between the bottom surface of the groove and the electronic component.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 4, 2021
    Inventors: Ho Hyung Ham, Jae Sung Sim
  • Patent number: 10939556
    Abstract: An electronic component embedded substrate includes first insulating layer having a first through portion; a first electronic component disposed in the first through portion; a second insulating layer disposed on the first insulating layer and having a second through portion; a second electronic component disposed in the second through portion; and an insulating material covering at least a portion of each of the first electronic component and the second electronic component. The first through portion and the second through portion intersect, such that a portion of the first through portion and a portion of the second through portion overlap each other, on a plane.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Sung Sim, Ho Hyung Ham, Won Seok Lee
  • Patent number: 10932368
    Abstract: A substrate-embedded electronic component includes a first core layer, a first through-portion penetrating the first core layer, a first electronic component disposed in the first through-portion, an encapsulant disposed in at least a portion of the first through-portion, and covering at least a portion of the first electronic component, a second core layer disposed on the encapsulant, and a first through-via penetrating the second core layer, wherein the first through-via is connected to the first electronic component.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ha Yong Jung, Ho Hyung Ham, Jae Sung Sim, Won Seok Lee
  • Patent number: 10849226
    Abstract: A printed circuit board includes: an insulating layer having a via hole formed therein; a single layer metal pad disposed in the insulating layer and having a center portion that is exposed by the via hole, the center portion of the pad having a higher roughness than peripheral portions of the pad; and a via formed in the via hole and connected to the center portion of the pad.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Mi-Sun Hwang, Hye-Won Jung, Jae-Sung Sim, Byung-Duk Na, Hee-Joon Chun, Sun-A Kim, Deok-Man Kang
  • Publication number: 20200312878
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-il CHANG, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Patent number: 10779409
    Abstract: A printed circuit board including: an insulating material; a metal layer stacked on a surface of the insulating material; and a via hole passing through the metal layer and the insulating material. The metal layer decreases in thickness in a region adjacent to the via hole, and an interface between the insulating material and the metal layer includes a region that is directed toward the via hole.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byung-Duk Na, Hye-Won Jung, Jae-Sung Sim, Mi-Sun Hwang, Hee-Joon Chun, Deok-Man Kang, Sun-A Kim
  • Patent number: 10700092
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang
  • Publication number: 20200178392
    Abstract: A printed circuit board includes: an insulating layer having a via hole formed therein; a single layer metal pad disposed in the insulating layer and having a center portion that is exposed by the via hole, the center portion of the pad having a higher roughness than peripheral portions of the pad; and a via formed in the via hole and connected to the center portion of the pad.
    Type: Application
    Filed: October 25, 2019
    Publication date: June 4, 2020
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Mi-Sun HWANG, Hye-Won JUNG, Jae-Sung SIM, Byung-Duk NA, Hee-Joon CHUN, Sun-A KIM, Deok-Man KANG
  • Publication number: 20200154568
    Abstract: A printed circuit board including: an insulating material; a metal layer stacked on a surface of the insulating material; and a via hole passing through the metal layer and the insulating material. The metal layer decreases in thickness in a region adjacent to the via hole, and an interface between the insulating material and the metal layer includes a region that is directed toward the via hole.
    Type: Application
    Filed: November 5, 2019
    Publication date: May 14, 2020
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byung-Duk NA, Hye-Won JUNG, Jae-Sung SIM, Mi-Sun HWANG, Hee-Joon CHUN, Deok-Man KANG, Sun-A KIM
  • Publication number: 20190296047
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-il CHANG, Jun-Hee LIM, Yong-Seok KIM, Tae-Young KIM, Jae-Sung SIM, Su-Jin AHN, Ji-Yeong HWANG
  • Patent number: 10367002
    Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: July 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Chang, Jun-Hee Lim, Yong-Seok Kim, Tae-Young Kim, Jae-Sung Sim, Su-Jin Ahn, Ji-Yeong Hwang