Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

Abstract: A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.

Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

Abstract: Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. Related structures are also discussed.

Abstract: Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors.

Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

Abstract: The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the active region appropriately, and it is a difference from the conventional art. The present invention induces electrons to band-to-band tunnel at the PN junction with the source/drain region by the multi-doped layers, and accelerates the electrons at the reverse bias to generate an avalanche phenomenon. Therefore, the method for operating a memory array of the present invention comprises programming by injecting holes which are generated by the avalanche phenomenon into multi-dielectric layers of each memory cells, and erasing by injecting electrons through an F-N tunneling from channels into the multi-dielectric layers of each memory cells.

Abstract: Refrigerator including a freezing chamber (1), a refrigerating chamber (2) at a side of the freezing chamber, a barrier (303) between the freezing chamber and the refrigerating chamber, the barrier having a freezing chamber cold air passage (A) formed therein, a partition plate (7) for compartmentalizing a freezing chamber cold air passage in rear of the freezing chamber where an evaporator (104) is positioned, the evaporator provided in a “” form along the freezing chamber cold air passage (A) and the refrigerating chamber cold air passage (B), a partition wall (9) between the freezing chamber cold air passage and the refrigerating chamber cold air passage, and a fan (305) mounted over the freezing chamber cold air passage and the refrigerating chamber cold air passage for discharging cold air flowing through respective cold air passage (10) to the freezing chamber and the refrigerating chamber respectively, thereby improving a cooling rate of the refrigerating chamber and providing more efficient refrigerat

Abstract: Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include selecting the unused memory cell, and programming the unused memory cell to have a predetermined threshold voltage. The charge-trap flash memory device may thus be provided with improved reliability by interrupting erasure stress to unused memory cells.

Abstract: Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation.

Abstract: A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.

Abstract: Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

Abstract: Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. Related structures are also discussed.

Abstract: A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns.

Abstract: A dual capacity compressor, which can maintain a fixed eccentricity and stable operation, even when the compressor is rotated in both the regular and reverse directions in order to provide multiple compression capacities, is provided. This dual capacity compressor implements an improved key member and associated key member fitting parts to inhibit relative motion of the crank pin and the eccentric sleeve during operation, so as to reduce or eliminate a destabilizing effect due to centrifugal forces on the eccentric sleeve and external forces applied through the connecting rod.

Abstract: A dual capacity compressor, which can maintain a fixed eccentricity and stable operation, even when the compressor is rotated in both the regular and reverse directions in order to provide multiple compression capacities, is provided. This dual capacity compressor implements an improved key member and associated key member fitting parts to inhibit relative motion of the crank pin and the eccentric sleeve during operation, so as to reduce or eliminate a destabilizing effect due to centrifugal forces on the eccentric sleeve and external forces applied through the connecting rod.

Abstract: A dual capacity compressor, which can maintain a fixed eccentricity and stable operation, even when the compressor is rotated in both the regular and reverse directions in order to provide multiple compression capacities, is provided. This dual capacity compressor implements an improved key member and associated key member fitting parts to inhibit relative motion of the crank pin and the eccentric sleeve during operation, so as to reduce or eliminate a destabilizing effect due to centrifugal forces on the eccentric sleeve and external forces applied through the connecting rod.

Abstract: Dual capacity compressor is provided to prevent relative movement between parts that maintain eccentricity. To this end, the dual capacity compressor comprises a power generating unit 20, having a reversible motor 21 and 22 and a crank shaft 23 inserted into the motor 21 and 22; a compressing unit 30 having a cylinder 32, a piston 31 and a connecting rod 33 connected with the piston 31; a crank pin 110 and 210 eccentrically formed on an upper end portion of the crank shaft 23; an eccentric sleeve 120 and 220 mounted between the crank pin 110 and 210 and one end of the connecting rod 33; and a key member 130 and 230 for completely restricting the eccentric sleeve 120 and 220 to the crank pin 110 and 210 in both clockwise and counter clockwise direction rotations of the motor.