Patents by Inventor Jae Ung LEE

Jae Ung LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250195578
    Abstract: The present invention relates to a culture medium for isolating and culturing urine-derived stem cells, a method for isolating and culturing urine-derived stem cells using the culture medium, urine-derived stem cells cultured in the culture medium, and a cell therapy product composition containing same.
    Type: Application
    Filed: April 19, 2022
    Publication date: June 19, 2025
    Inventors: Hong-Ki LEE, Seong-Hun LEE, Sang-Heon KIM, Jeong-Ah JIN, Tae-Wook KANG, Hyung-Joon SO, Su-Bin SO, Kyu-Sung JUNG, Jae-Ung LEE, Jin-Sang YOON, Young-Jun LEE
  • Patent number: 12187603
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: January 7, 2025
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
  • Publication number: 20240395771
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
    Type: Application
    Filed: August 5, 2024
    Publication date: November 28, 2024
    Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
  • Publication number: 20240332159
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Application
    Filed: June 4, 2024
    Publication date: October 3, 2024
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Patent number: 12057434
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: August 6, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
  • Patent number: 12009289
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: June 11, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Publication number: 20240088059
    Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent to the package body, which is electrically connected to the conductive spaced-apart pillar structures.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Young Woo LEE, Jae Ung LEE, Byong Jin KIM, EunNaRa CHO, Ji Hoon OH, Young Seok KIM, Jin Young KHIM, Tae Kyeong HWANG, Jin Seong KIM, Gi Jung KIM
  • Patent number: 11855000
    Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: December 26, 2023
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Young Woo Lee, Jae Ung Lee, Byong Jin Kim, EunNaRa Cho, Ji Hoon Oh, Young Seok Kim, Jin Young Khim, Tae Kyeong Hwang, Jin Seong Kim, Gi Jung Kim
  • Publication number: 20230257257
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 17, 2023
    Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
  • Publication number: 20230118400
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
    Type: Application
    Filed: October 31, 2022
    Publication date: April 20, 2023
    Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
  • Patent number: 11572269
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: February 7, 2023
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
  • Patent number: 11488934
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 1, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
  • Publication number: 20220302043
    Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Young Woo Lee, Jae Ung Lee, Byong Jin Kim, EunNaRa Cho, Ji Hoon Oh, Young Seok Kim, Jin Young Khim, Tae Kyeong Hwang, Jin Seong Kim, Gi Jung Kim
  • Patent number: 11355449
    Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: June 7, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Young Woo Lee, Jae Ung Lee, Byong Jin Kim, EunNaRa Cho, Ji Hoon Oh, Young Seok Kim, Jin Young Khim, Tae Kyeong Hwang, Jin Seong Kim, Gi Jung Kim
  • Publication number: 20220051973
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 17, 2022
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Publication number: 20220009968
    Abstract: The present disclosure relates to a composition for enhancing the cell permeability and gene correction efficiency of Cas protein and guide RNA. The currently used CRISPR-Cas-based gene correction technology has the problems of difficult intracellular injection in a complex form, unverified stability and low efficiency even after injection, and the off-target problem. In contrast, the composition for gene correction of the present disclosure can be usefully used for gene therapy due to remarkably high intracellular delivery efficiency, inhibited off-target, and ensured stability.
    Type: Application
    Filed: December 27, 2019
    Publication date: January 13, 2022
    Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Je-Min CHOI, Ja-Hyun KOO, Hong-Gyun LEE, Jae-Ung LEE
  • Patent number: 11152296
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 19, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Publication number: 20210217725
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
    Type: Application
    Filed: December 21, 2020
    Publication date: July 15, 2021
    Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
  • Publication number: 20210047172
    Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
  • Patent number: 10872879
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 22, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi